Also I'm interested in using DP83867 PHY from TI, how can I make sure this core support this PHY?
MAC layer is generally PHY-agnostic as long as it supports the right protocol (GMII, RGMII, SGMII). There are differences in initialization protocol for different PHY chips, but they are commonly handled at the software level within PHY-specific driver.
As far as the PHY protocols go, SGMII is by far the simplest to route, but there are some gotchas - like with Artix/Spartan-7 when you have to have Vccio of 2.5 V in order to use LVDS, or 1.8 V if you want to mess with ac-coupled DIFF_HSTL, not to mention that routing 1.25 Gbps differential pairs requires some experience with high-speed layouts. With that, I only recommend going for this standard for experienced designers. That said, Xilinx provides a free SGMII-to-GMII IP core, so you can connect any GMII core to SGMII PHY via that core.
Now, RGMII has it's own share of idiosyncrasies. For example, some RGMII PHY chips have internal clock delay (they sometimes are called "RGMII v2.0"), others require this delay implemented externally - either on a PCB with clock line being artificially longer than data lines, or inside MAC. So the easiest option is full-on GMII, but it's got quite a number of traces which need to be length-matched.
As for the MAC itself - why not roll out your own? It's not very complex (IO being probably the hardest part), and it's fun project which can be as simple or as complex as you want - from AXI-steram-to-R/S/GMII using AXI DMA IP on the simple end, all the way to built-in SG DMA master with HW CRC offload and timestamping support on the complex end.