FPGA

Lattice CrossLink NX EVB Clocking w/higher speed clocks

del

Sorting out 'Unbuffered IO' warnings for Lattice ICE40 Ultralite devices

Partial reconfiguration of FPGA on the fly

« 1 2  All »

Cyclone IV PLL not working correctly

USB3320 Device not able to detect with Zynq RFSoC

« 1 2  All »

Xilinx: interface microblaze to hard IP

Alternative for Lattice 4032ZE?

Quartus ALTFP_SQRT IP not working in simulation

Efinix Trion FPGA's

« 1 2 3  All »

Need driver for XUPV2P board

Gowin triple speed ethernet MAC. Trouble with tx data

Ideas on what type of JTAG device to purchase

Terasic DE5-NET

Interfacing peripherals that run on different clocks.

Simultaneous read/write with Quartus-|| single clock FIFOs

Trouble shooting ZCU111 RFSoC board

Loading FPGA configuaration from SPI flash

Disciplined signal clock to PPS

Zynq Quad SPI controller: has anyone used it successfully for non-flash devices?

New Verilog: Incrementing without getting continous assignment conflict

Using embedded I2C in Lattice MachXO2 as DS3231

Gowin: Which programmer to use?

Re-enabling JTAG in Altera Max3000A PLDs

How to add in Verilog? Quartus, EPM7064STC44 etc.

Xilinx ISE 14.7 - IMPACT is a disaster

And the warning is gone ... Simple DivClk by N

Elegant way to select output type from a register or wire ?

Reset in Verilog isn't working as planned

Should I use one big always block or several smaller ones?

Best FPGA for the job - low-speed LVDS deserializer

Basys 3 Pmod Tips

A 5V CPLD in 2023?

LPDDR4 memories

Anyone else misses jtag_loader?

timed state machines VHDL

« 1 2  All »

TVS diodes in FPGA development boards

DDR3 Data capture using ISERDESE2

EBAZ4205 questions / problem

Newbie starting using FPGA