Electronics > FPGA

3 bit Dff Counter Issue

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jrw0531:
Hello all,

Overall project: getting a 555 timer to power a stepper motor with 7400 logic only. I've decided to try a 3 bit counter with D flip flops but I am not getting the desired output.
My desired output is a half step of a stepper motor, so A, AB, B, BC, C, CD, D, DA but I am getting some weird results in my simulation. TIA! I've checked my K-map process and output logic multiple times and I don't think that is the issue. Attached is schematic and waveform.

BrianHG:
In your simulation, you should also display your 3 bit counter's output so you may see if it is counting properly.  This will help you debug.


If you are designing to eventually place this logic in a PLD:

I'm curious.  You appear to be using an old quartus schematic entry, manually entering gates and wires.

Would you not prefer to do this in an HDL language like verilog or System Verilog?

It would be much easier to code, simulate and edit as you are talking about a basic setup, then very few lines of code.

Also, you may use a proper simulator like Modelsim which is also available for free with Quartus as well as for most other FPGA vendors.

BrianHG:
If you want to stick with the 74xx logic, maybe instead of using 3 DFFs as your counter, try using a 4bit UP-Down counter.  This way, you at least know your counter logic itself is sound.

Maybe look at the 74LS169.

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