FPGA

Gating the clock

ice40 ultra icecube2 software does not recognize my input constraint

Simulating Memory in verilog

Cyclone III EPC4 flash - programming off board

FPGA to softcore or hardcore data stream bus

Phase sync two same frequency input's ?

ice40 Hx8K project not configuring from external flash

« 1 2  All »

$20 FPGA board with 2x8 PCIe and 2x QSFP

FPGA based SSDs

Jtag with Wiggler

Indexed pins in constraints file?

How to simulate/testbench with IceStudio?

DE10-Lite Problems with 7-Segment Display

Original SiLego Mixed Signal FPGA Legacy- Old Software?

Comparing performance of genuine vs cloned programmers for Intel/Altera FPGAs

Best replacement for AMD/Xilinx CPLDs XC9500

« 1 2  All »

VHDL Port Declaration issues in Lattice Diamond

Vitis 2023.1 would not open after crash

XILINX cse_server on win10

New FPGAs from Renesas

« 1 2 3 4 5 6 7  All »

Xilinx DDR Controller Strange Behavior in Sim

Any clue with this HDMI IC Chip is = "TC9138A" (QFN package)?

Custom Spartan-7 FPGA board for beginners

« 1 2 3 4  All »

Forth (e.g. Mecrisp-Stellaris) on a Zynq?

« 1 2  All »

Driving an LVDS LCD

« 1 2 3  All »

FPGA development board with MIPI

No more Xilinx CPLDs and Spartan 3s

CPLD passthrough in ISE

VexRISC V - increasing pipeline depth

Quartus issue - Nios 2 Software Build Tools for Eclipse crashes on startup

Why cant I add a 5th state to my state machine?

iCE40UP - how to select SPI Master config mode?

First design with FPGA, DDR4 and Hyperlynx SI simulation

Are GreenPack SPLDs logic prone to glitches?

Help finding a small and low cost programable logic IC.

« 1 2 3 4 5  All »

Pango Micro FPGAs?

What the hell is up with Vitis HLS.

MCU with FPGA vs. SoC FPGA

« 1 2 3 4 5 6 ... 8  All »

Arcade game repair