Electronics > FPGA

5v Fpga Hypothetical Question

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pacmann:
VCCO max for Spartan 6 is 3.75v. What exactly happens if the Fpga is run at 4v or 4.5v for example :-/O, to make it compatible with 5v cmos levels? Assuming the Fpga isnt doing anything high speed, is it a thermal problem? Is it shortened life problem because of transistors breaking down? I dont recommend this to try, only wondering what happens..

Mario87:
Something will likely fail short circuit within the device if run at 5V as the insulation breaks down. This may happen immediately or slowly over time, but regardless, it's not something I would try. If you need to communicate to devices which use 5V CMOS levels then just use a level shifter to go between the 3.3V of the FPGA and 5V of the device. Safer and much more predictable as to what will happen both long and short term.

SiliconWizard:
Most often, 3.3V logic in CMOS processes supports something like 3.9V as an absolute maximum.

What will happen if you exceed this is oxide breakdown. Transistors's characteristics deteriorate. The higher the "overvoltage" and the shorter this process will take, until complete dysfunction.

I have seen some reliability studies for typical CMOS processes that would show a typical lifetime reduction of several orders of magnitude when powering 3.3V logic @ 1 V to 2 V above the absolute maximum rating. That's definitely not very pretty.

langwadt:

--- Quote from: SiliconWizard on August 01, 2021, 05:55:58 pm ---Most often, 3.3V logic in CMOS processes supports something like 3.9V as an absolute maximum.

What will happen if you exceed this is oxide breakdown. Transistors's characteristics deteriorate. The higher the "overvoltage" and the shorter this process will take, until complete dysfunction.

I have seen some reliability studies for typical CMOS processes that would show a typical lifetime reduction of several orders of magnitude when powering 3.3V logic @ 1 V to 2 V above the absolute maximum rating. That's definitely not very pretty.

--- End quote ---

some Xilinx FPGAs turn off the supply to the output transistors if the Vcco goes above ~2.9V on outputs  configured
as LVDS because those transistors can't even handle 3.3V

David Hess:
Over time, hot carriers generated in the channel from the higher electric field damage the interface and gate oxide altering the drain current,  threshold voltage, and transconductance, so there is a gradual deterioration of the device characteristics. 

A high electric field across the gate oxide damages it over time increasing the threshold voltage and gate leakage.  Eventually the gate oxide suffers catastrophic breakdown.

I suspect these effects are exponential with respect to the applied voltage so for example an increase of 50 millivolts might halve the operating life.

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