FPGA

More Efficient MAC operation

Xilinx FPGA Drive Strength Explanation

Verilog Floating Point Clock Divider Release.

Intel Quartus Prime Pro - How is Modelsim-Altera supposted to work?

XC9500XL : using a GCK pin as regular IO to match long transition time clock

Terasic DE5-NET

FPGA based I/Q generator

TinyTapeout

AES 256 FPGA core

Xilinx: interface microblaze to hard IP

Terasic FPGA Dev Board - Altera DE2-115 vs SoCKit

Quick question on Quartus support

Should a new EPM3064A be 'blank'?

FPGA DSP filter to convert 16bit words to 10bit words at higher sample rate

Address decoder

Issue with implementing data processing in VHDL code

Trying to workout `ifdef syntax to assign a specific localparam in SystemVerilog

Gigabit Ethernet Example code

Moving design between different variants

Issues programming TinyFPGA AX2

Ideas on what type of JTAG device to purchase

Machx03 I2C programming

Programming local FPGA from remote desktop conenction

Custom SDR + optical fiber

Avnet for Xilinx XC3S400A

PMIC for Z7020

Flash devices for FGPA

Tools for programming 16V8 GAL

[Lattice Diamond] Which available simulator?

Programming device for MACHXO2?

I don't understand MachXO2 programming mechanism

Verilog coding style guidance needed

Help with this verilog video

"buy cheapest fpga board you can find" - i struggle to find tutorials (ISE)

Advice on an imaging project

Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx I

iCEBreaker bitsy project status

Xilinx ISim: Display I2C as hex in simulations?

Project idea: GSP referenced clock.

Spartan-3 Family dead in 2021?