FPGA

DE10-Nano JTAG broken?

Good intros to FPGAs?

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FPGA Delta-sigma modulator IP

FPGA DSP filter to convert 16bit words to 10bit words at higher sample rate

Best FPGA for the job - low-speed LVDS deserializer

Any Open Source Tools for Lattice ispMACH 4000?

Tang Nano 9K FPGA Board - No USB Cable Connection

VHDL assigning to and from array gives "XXXX"

inout with physical pins in Verilog

Protecting against bus contention in prototype

anyone need this part XILINX XCVU440-2FLGA2892E

[FPGA] From zero to DVB parsing

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Book on SMPTE SDI Protocol?

FPGA Xilinx XC3S400A

Xilinx 7-Series vs. Efinix Titanium/Topaz for PCIe endpoint

IC configuration approach - Hardware vs. software

MCU with FPGA vs. SoC FPGA

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Analog video output with FPGA ?

How to config the AD9517-3 registers(fine delay ) to produced 180-degrees output

problem with LVDS Oscillator on Zynq borad !!!!!!!

Xilinx PLL Mamimum output frequency

poblems with capturing the sine wave in xilinx chipscope!

Max 7000 vs ATF1508 Issue

VHDL: input signal timing variations

GAL16V8 and wincupl: replicate an output

Quartus II v13.0.1 MAX7000S Bidirectional Pins

JTAG Programming on PLUTO PLUS or ADALM Pluto

Intel Altera Cyclone IV - not startup

SERDES pronunciation?

Where are gowin FPGAs available for an actually reasonable price?

Alternative programmers for Microchip/Atmel ATF1500 series CPLDs?

ATF15XX Dev DK2 example file PLDs etc

FOR SALE: Altera Terasic DE1 Development Board Kit

Lattice XP2 programming tool

clocking scheme/CDC for half-band filter

Lattice CrossLink NX EVB Clocking w/higher speed clocks

Xilinx Spartan 3A availability

Lattice XP2 DCS issues

FPGA Clock (setup slack) issues.

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Does anyone know how many times an Altera MAX II CPLD can be reprogrammed?