FPGA

tRAS definition for DDR memory

Looking for Easy-ABEL v4.x documentation (PAL, GAL)

Tasks in Verilog on Clock edges

No pulse in CLK test points

Design cascaded sinc filters, how to?

Metastability synchronizer or positive and negative clock edges?

Old Altera flex10K, looking for a board schematic

Disciplined signal clock to PPS

FPGA LVCMOS vs LVTTL standards

Spartan 6 Bitstream Configuration Protection

Zynq and device drivers in Linux for custom peripherals designed in VHDL

Cheapest zynq system-on-module?

Vivado: Synthesis crash (address violation) at "Start Cross Boundary" stage

US and Canada only. Win a Digilent Zybo dev board for the Xilinx Zynq 7000.

Verifying RISC-V compliance

Reason for Synopsys Synplify, MG Precision when Quartus/Vivado are free

Altera Dual Port RAM bytes shifting error

Critique of first design

Quartus 21.1 Free Edition - Confused about free to use IP

Newbie starting using FPGA

Altera Cyclone II mini board: why hardwire external pins?

Verilog Assign Logic to Wire Array?

Cheap USBBlaster clone and Altera Signaltap

open source USB OTG core?

How to Get Support When You Can't Contact Support?

Where to start with FPGA PCB design?

Modern replacement for Altera EPM7064LC84-15

Lattice IP use with Modelsim

Need decode the 8B10B data sequence of 1.3Gbps speed within Lattice FPGA LFE-5UM

Suspiciously cheap Xilinx Virtex on ebay

How in the world do i get started

FPGA SPI Timer, help needed

Opening Gowin VCD files in Questa sim

Multiported RAMs [SOLVED]

How to program 82S100 devices

Machx03 I2C programming

Learning how to deal with FPGAs

Soft CPU tools

(book) Pipelined Multi-core MIPS, Implementation and Correctness

Program Cyclone IV with USB blaster from arm64 linux