FPGA

Xilinx ISim: Display I2C as hex in simulations?

Altera De0 board opinion

Spartan 6 Bitstream Configuration Protection

Arty A7-35 Dev Board, timing issues in design

generating Verilog from a schemetic (ICESTUDIO code versus DIGITAL code)

FPGA: Please help set up set_output_delay constraints

Microchip Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC

FPGA Verilog Project - Saving values for future processing

I am looking for help completing an FPGA project or two.

"buy cheapest fpga board you can find" - i struggle to find tutorials (ISE)

FPGA Algorithm Projects

Lattice iCE 40 FPGA distorted clock signal

Advice on an imaging project

Alternative for Lattice 4032ZE?

Help with this verilog video

[Lattice Diamond] Which available simulator?

Active-HDL 10.5 - VHDL assignment woes

Project idea: GSP referenced clock.

Playing with old XC3000A + XACT 5.2.1... no pins assigned or routed

Verilog coding style guidance needed

Varying Verilog code simulation results in "Xilinx Vivado" compared to "Xilinx I

Spartan 6 production through 2030

JESD204B over fiber

Xilinx Ethernet Network Client 101

A7-FTG256: Decoupling caps on unused banks

Programming CPLD

Simulate Xilinx libraries on Vivado

Altera FIR compiler not using embedded multipliers

Xilinx ISE license through University Program

Verilog UART doubt

Memory mapped SPI Dual port Ram

If Lattice iCE40UltraPlus has DDR primitives like ODDR in Xilinx?

MAC for xilinx FPGA

resources needed on how to build a synthesizable pipeline in verilog

DPSK demodulator circuit

Xilinx project no longer generating good binary - what have I done wrong?

Spec-ing ADC to interface with FPGA

Draw Arc in Verilog

I don't understand MachXO2 programming mechanism

Programming device for MACHXO2?