FPGA

Arctan calculation on FPGA

reading csv file for test-bench in verilog

IMPACT : Can't open /dev/parport0: No such file or directory

Xilinx SDK - preconfigure DDR with data?

Switching read & write between memory banks with a flag (verilog) - timing issue

Verilog UART doubt

PWR up sequence for new design using ICE5LP4K

Atmel ATF150x CPLD and WinCUPL

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Vivado - strategies for resolving timing errors

FPGA + FT232H

lockup latch issue

48-bit unsigned integer to 32-bit IEEE-754 float for Xilinx 7-series (VHDL)

ICE40 Board Design review

Anyone that moved from VHDL to SystemVerilog, what advice do you have for others

PMOD I2S2 codec attenuation with Cyclone IV

WinCUPL - need to create a 10ns delay

S_AXI_AWREADY always red X in Vivado simulator

DDR sdc commands

How SDC definition affects synthesis result?

Intro using Xilinx Artix7 MIPI CSI IP

softcore: getting started

Openocd with DE-10 nano (usb blaster 2) [Solved]

What is this board with ten Virtex FPGAs on it?

FPGA Beginner question...would an FPGA have enough gates to perform this?

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How to create SPI slave in FPGA when SCLK frequency similar to FPGA system clock

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EBAZ4205 (Zynq-7000 based development board)

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Xilinx Ethernet Network Client 101

Cyclone IV GX EP4CGX22 LVDS pins

Incrementing a counter in Verilog

Numato Labs Mimas A7 Mini FPGA Development Board - your experiences?

Serializing: shift registers vs. multiplexers

Alternatives to always@(posedge clk, negedge clk)

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How to feed an int to a third party module which wants a parameter in "Quotes"?

Vivado - ports not connected in implemented design

VHDL Case Statement

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Memory mapped SPI Dual port Ram

Xilinx SliceM LUTs as distributed RAMs: read-first, write-first, or selectable?

Multiported RAMs [SOLVED]

What is wrong with my if-else statment in this VHDL code for a counter? [SOLVED]

Lattice ECP5: opinion?

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