FPGA

Active-HDL 10.5 - VHDL assignment woes

Playing with old XC3000A + XACT 5.2.1... no pins assigned or routed

Verilog coding style guidance needed

I don't understand MachXO2 programming mechanism

Programming device for MACHXO2?

Microchip Opens Early Access Program for RISC-V Enabled Low-Power PolarFire SoC

Spec-ing ADC to interface with FPGA

Reason for Synopsys Synplify, MG Precision when Quartus/Vivado are free

Detect Protocol on bus

Xilinx ISim: Display I2C as hex in simulations?

Questions about Lattice MachXO

[Lattice Diamond] Which available simulator?

Need help with XDMA Stream

Vitis 2023.1 would not open after crash

RS-232 on ice40 UP5k

Timing issue.

Is my petalinux image too big?

Verilog blocking statements in always block (SOLVED)

CycloneIV registers - infer use of both clock ENA and synch clear SCLR

2nm Chips

Interfacing peripherals that run on different clocks.

New Verilog: Incrementing without getting continous assignment conflict

Spartan 6 IP Camera Question

New Gowin IDE does not detect my DIY JTAG adaptor any more

The VHDL poster you didn't know you need

Stupid question - what does axis mean?

EnterPoint RaggedStone1 Files

reliable clock detect and reset signal generation in verilog

Old Altera flex10K, looking for a board schematic

Max 7000 vs ATF1508 Issue

Help with Altera Cyclone III configuration problems.

ICE5LP4k SG48 voltage feeding through IO pin 48

Does anyone know how many times an Altera MAX II CPLD can be reprogrammed?

Free softcores usage: XILINX x ALTERA

Goldschmidt Division

Gowin Vs. Yosys

anyone need this part XILINX XCVU440-2FLGA2892E

Verilog generate and buses

Net "clk50" not found - only after adding extra "process" block (VHDL, Xilinx)

Xilinx ISE - USB cable setup