FPGA

RAM timing problems (SOLVED)

Looking for instant on FPGA or CPLD for a current project

LFSR

[Zynq] transferring data between CPU cores and fabric without too much hassle

New Efinix FPGA family - Topaz

xilinx Z7 (7Z045) control chip warms up quickly at boot time

FPGA internal logic analyzer

Verilog - elegant solution for variable width definition

Gowin FPGAs: What is equivalent of "AXI Bus" (Xilinx) in Gowin's IP Cores

How to feed an int to a third party module which wants a parameter in "Quotes"?

Counting in state-machines

Mystery routing in Xilinx FPGA - unconnected connected block of FIFO?

Best and Worst HDL Features

Memory mapped SPI Dual port Ram

Or-ing std_logic_vector of dynamic sizes

FPGA development board with MIPI

Optimizing MUXes

EnterPoint RaggedStone1 Files

Numato Labs Mimas A7 Mini FPGA Development Board - your experiences?

HDL code for positive edge triggered J-K flip-flop with preset and clear

Help me choose a starter kit

Avnet for Xilinx XC3S400A

GreenPAK SPLD blinky?

VHDL: input signal timing variations

Xilinx bare metal USB issue

VHDL Port Declaration issues in Lattice Diamond

113 and increasing weekly blogs on the Xilinx Zynq

Complete newbie

True Dual-Port memory verification

USB to multichannel PCM

usb verilog softcore questions

Spartan 6 IP Camera Question

A simple Clock Domain Crossing (CDC) strategy

Attempting to identify mysterious PAL Hardware Description Language

Lattice Diamond 3.12_240 painfully slow startup on Debian 11

Altera EPM7096 Quartus II support?

Xilinx 7-Series vs. Efinix Titanium/Topaz for PCIe endpoint

verilator width warnings

Custom JTAG debugger for Xilinx FPGAs based on FT22x chips

Gowin: JTAG device detection failure (pretty scope pictures included!)