FPGA

Xilinx ISE Microblaze tutorials or examples available?

FPGA :how relevant is HDL based development??

FPGA (Verilog) - RGB pixels to SDRAM using FIFO

Xilinx clocking wizard - Requested frequency vs actual frequency

Gowin FPGA - MIPI Display

Need help debugging SDRAM controller

FPGA high speed data processing?

OpenCores.org login

Help me choose a starter kit

Software for ACTEL FPGA A1020A ?

Programming Flash on Spartan 3E Starter Kit

Gowin M3 CPU usage with FPGA fabric

Xilinx XC9536XL CPLD with Alterra USB Blaster

Vintage Altera

Metastability synchronizer or positive and negative clock edges?

Port <i_Clk50MHz> has illegal connections.

FPGA prices WTF

Lattice iCECube Licensing key

Turn off name mangling during Vivado behavioural simulation

Lattice ICE40 instantiating RGB/IR pins as regular user IOs.

Net 'myled' does not have a driver?

UART rx is not properly working

8-bit retrocomputer: MMU + VIA from a PLD: ATF2500C-20PU?

USB NRZI data encoding

Xilinx Vivado download pain

Selecting pin impedance on fpga

clock recommendation for Xilinx XCR3064XL (3.3v) or Altera Max 7000s (5v) CPLD

Verilog right shift help

SERDES pronunciation?

How to pipeline DSP48 input?

Help with converting old PALs to GAL

Artix-7 GTP transceiver as delta-sigma DAC

How can I kill this bug in my Data logger Code?

CPLD/FPGA design flow

Newbie with Vivado and XMD Console questions please?

How to drive wheel on FPGA?

Intel replaces their NIOS II soft core in their FPGAs with 5x faster NIOS V RISC

Low power CPLDs alternatives?

Xilinx Artix 7 Bitstream Encryption Fix?

Ft2232h fifo realtime data stream