FPGA

NEORV32 soft-core CPU (RISC-V) - bootloader is not working

anyone need this part XILINX XCVU440-2FLGA2892E

Low power CPLDs alternatives?

Very simple FPGA for ADC 12-bit

Used Bittware board

Xilinx MPSoC and RFSoC, what is the big deal?

PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20

Xilinx Transceivers

Looking for good 32 bit pseudo RNG in SystemVerilog.

ICE40up pll with external clock howto ?

Debouncing technique for a SPDT switch connected to CPLD

Looking for an editor / IDE that understands verilog

ABEL to VHLD conversion

ALU in MIPS

Simulate Xilinx libraries on Vivado

IMPACT : Can't open /dev/parport0: No such file or directory

Searching for Quartus 14.0 installer [solved]

Which Cyclone PLL implementation is better?

Tindie.com & Micro-Nova order frustration (it finally arrived!)

Quartus II 18.1 light problem getting functional simulation to work.

Undergraduate thesis and FPGA

Xilinx XC2018. Useful or rubbish?

FPGA based Direct Digital Synthesis

FPGA Verilog Project - Saving values for future processing

FPGA USB3.0 Mass Storage mode?

Vivado for Windows, what do I need

Book on SMPTE SDI Protocol?

Correctly handling clocks on a older Cyclone IV

Anyone tried Renesas ForgeFPGA ?

Efinix T4 F49 WLCSP Package SPI Flash programming

Usage of the word 'strobe'

Xilinx Ethernet Network Client 101

VCD to CSV Conversion

Lattice Certus-NX PCIe, or alternative

What has happened to my Vivado Project?

verilog conditional compilation with several flags in condition

Two basic GreenPAK SLG46826 SPLD questions

Why wide demux allows the partitioning of memory bandwidth to be able to change

Has somebody tried TCL scripts with "Gowin EDA" (Gowin FPGA Designer)

REQ: AVNET SPARTAN-6 LX9 Microboard Files