FPGA

FPGA based Direct Digital Synthesis

Interfacing LVDS laptop screen with fpga

True Dual-Port memory verification

PALCE programming algorithm

FPGA failure modes

FPGA based I/Q generator

low-jitter timing generation using FPGA

Sine Wave on FPGA

How CORDIC sin/cos in HDL works.

8-bit retrocomputer: MMU + VIA from a PLD: ATF2500C-20PU?

Waveform generation on FPGA

HDL Code formatting.

Looking for Xilinx Foundation 2.1i, 3.1i software.

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FPGA output not consistent with ModelSim

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Any tutorial on AXI PS-PL interop for the latest version of Vitis?

Gowin MiniStar Nano Limited Edition

GOWIN FPGA

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Specific to the group but slightly off topic

Timing issue.

High speed bidirectional MPU interface

What is a better write enable

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EPM240T100C5N -> Fitter requires XX LABs to implement the project but the device

Inferring block RAM

Quick question on Quartus support

Why does this dds code fail (Solved)

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[Solved] Cyclone V (de10-nano) SDRAM controller - how to reserve memory for FPGA

WTB cheap low-end evaluation board and cables

CSI-2

FPGA project where clock for it is external signal - what rules for designing?

Pixel to byte

VHDL Code to Verilog Code

What is the proper way to invert and tie high/low, signals in the Vivado IP inte

Address decoder

Basic Serializer Verilog

Hacking surplus Pano Logic thin clients

LDPC soft decoding - a breadcrumb trail for others.

Python Modules/Libraries?

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Help, how to program TMS32F2812GHHA

TL866II+ - what to select to program PALCE22V10H ?

STA timing closure for asynchronous FIFO