FPGA

IceStudio with Ice40 UltraPlus Breakout

Spartan 6 Bitstream Configuration Protection

Trim Unwanted logic from Xilinx IP

FPGA Active Open Source Projects

« 1 2  All »

Verilog blocking assignments

DE10-Nano JTAG broken?

Testbench waveform creator application?

GOWIN FPGAs

USB to multichannel PCM

Altera Cyclone II mini board: why hardwire external pins?

Gowin B-SRAM Bit Ordering

Ft2232h fifo realtime data stream

Open source FPU with 1 cycle performance

« 1 2  All »

GAL16V8 and wincupl: replicate an output

Do you know why this code Keeps crashing!

ICE40up pll with external clock howto ?

Xilinx SP605 evaluation board question on ISE support

Looking for an editor / IDE that understands verilog

Vivado/Vitis 2020.2 is out

MUXes or tristate for busses?

5-stage pipelined CPU and synchronous memory access

Opening Gowin VCD files in Questa sim

Can anyone program a PLS153 or a 82S153 from a good part/

Is there any significant speed difference between Cyclone IV and 10?

How to calculate fanout_latency for set_clock_gate_latency ?

Pls suggest small cheap FPGA with 3Gbps tranceivers

« 1 2  All »

JESD204B IP core on Artix FPGA

Edgeboard lite

Lattice Dev boards more than double the price since 2019?!

[Zynq] transferring data between CPU cores and fabric without too much hassle

AMD Reportedly In Advanced Talks To Buy Xilinx for Roughly $30 Billion

« 1 2 3  All »

Cant find the latch in my state machine

iCE40HX4K

Combinatorial inside or outside of a process

« 1 2  All »

Kintex XC7K325T for $45

VHDLWhiz Advanced Course Sign-up

Use Microsemi/Microchip IGLOO in new design, will they have future ?

set_{input,output}_delay for external bus

Software for ACTEL FPGA A1020A ?

Getting Started with a Alinx AN108 and Cyclone 2 Board Help