FPGA

Altium NanoBoard-NB1 without Altium Designer Software

VHDL assigning to and from array gives "XXXX"

Student classes and using block diagrams

Low power CPLDs alternatives?

Xilinx XC3S1200 Bitstream - Microblaze pack extraction

State Diagram Application

Running Xilinx Vivado HLS from in the Cloud - Can it be done?

How to generate pseudorandom bit sequence in FPGA?

LFE5UM5G-85F-LMP-EVNG

VERILOG: Equality test with don't cares

Heavily configured FPGAs

PALCE Chips

FSM Case Statements

VexRISC V - increasing pipeline depth

So what's a TQGA144 (Xilinx Spartan 7)?

Verilog "output" vs "output wire"

Verifying RISC-V compliance

[Constraints 18-5210] No constraints selected for write.

Numato Labs Mimas A7 Mini FPGA Development Board - your experiences?

Reset - Sync, Async or None At All

Altera A-C2FB kit ( board documentation )

EEPROM Programming - ST M29F400BB TSOP48 Package Help Please!

softcore: getting started

Critique of first design

Kintex-7 board - good deal?

Alchitry Cu problems

iCE40HX4K

An open source Xilinx Spartan 6 miniPCIe development board

Efinix Trion T20 MIPI Tx LS question

Audio DSP algorithms

USB to multichannel PCM

Cyclone III EPC4 flash - programming off board

Here is something I built for my own enjoyment.

What am I doing wrong?

clock divider circuits / how would you design them without just copying?

Gowin Arora V SRAM Based FPGAs

Q on Verilog use of GPIO pins on Gowin Ministar EVB

S_AXI_AWREADY always red X in Vivado simulator

EP2C5/EP2C8 Mini Board

Home made Xilinx parallel cable III not working