FPGA

Kintex-7 FPGA board with DDR3 memory and pci-e

« 1 2  All »

Vivado is shit at timing optimization?

« 1 2  All »

Artix-7 GTP transceiver as delta-sigma DAC

Xilinx ISim: Display I2C as hex in simulations?

FPGA Training Courses? Vivado and SystemVerilog?

5v Fpga Hypothetical Question

« 1 2  All »

Need help with Altera NIOS II processors.

Should I use one big always block or several smaller ones?

Questions about Lattice MachXO

Low power CPLDs alternatives?

Running Xilinx Vivado HLS from in the Cloud - Can it be done?

Xilinx SDSoC development environment - is it free or how much does it cost?

Best value for money FPGA board with Xilinx Zynq-7000 All Programmable SoC

Zynq and device drivers in Linux for custom peripherals designed in VHDL

Arcade game repair

Reverse engineering Anlogic AL3_10 FPGA

« 1 2 3 4  All »

What is a better write enable

« 1 2 3  All »

Why does this dds code fail (Solved)

« 1 2 3  All »

Latest version of Anlogic IDE?

Spartan3e with BPI flash

PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20

Python Modules/Libraries?

« 1 2  All »

CPLD divide by 1.5 50% duty cycle

Tools for programming 16V8 GAL

Review of FlashLINK JTAG interface

What are FPGAs used for today and with what tools?

« 1 2  All »

Xilinx FPGA Drive Strength Explanation

Xilinx Ethernet Network Client 101

Suggestions For Communication Between Multiple FPGAs

Spartan 6 Bitstream Configuration Protection

Configuring Multiple Xilinx FPGAs From 1 SPI Flash?

Lattice MachXO2-7000 DDR SDRAM

Looking for Enterpoint development board manuals

Kintex-7 board - good deal?

Correctly handling clocks on a older Cyclone IV

FPGA SDR Training - Dev boards

Xilinx clocking wizard - Requested frequency vs actual frequency

Cyclone IV GX EP4CGX22 LVDS pins

Altera MAX 10 accessing lpddr2 sdram

Best RETARGETABLE C compiler for FPGA CPU projects?