FPGA

Power Consumption of Cyclone IV on each voltage rail

FPGAs using a wireless camera?

GOWIN FPGAs now in stock at Mouser

Programming device for MACHXO2?

How to generate pseudorandom bit sequence in FPGA?

Quartus tcl LogicLock member

State Diagram Application

How Many Blocks Do You Use When Designing a FSM?

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Verilog "output" vs "output wire"

Converting table files (.tbl) to vector waveform files (.vwf) for simulation.

I don't understand MachXO2 programming mechanism

Converting a two level analog signal to two bits digital in Cyclone IV or/and V

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Cyclone 5 recovered from scrap boards

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Xilinx's "Device Lookup" Service

Learning how to deal with FPGAs

Home made SystemVerilog 3 word, Zero latency FIFO, documented for beginners.

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New FPGA manufacturer - German Cologne Chip

Net 'myled' does not have a driver?

2nd Order Sigma-Delta Digital to Analogue Converter (SD-DAC) in Verilog

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Xilinx ISE - how to improve erratic timing optimization?

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How do I write VHDL that can keep up with a 6.6Gb/s GTP?

Programming CPLD

Spartan-6 DCM_CLKGEN -- unexpected derived timing constraints

FPGA ide, currently using quartis 2

Quartus M10K ModelSim fails

Picking a "core frequency" for a FPGA

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Getting a Verilog PS/2 interface working

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Altera configuration Flash - crazy prices - alternatives?

Using code to remove bounce

Tasks in Verilog on Clock edges

Spartan-6 CCLK switching to 50 MHz -- why?!

Counting in state-machines

How to hack the EP1K30TC144-3N ?

ADC with Altera Cyclone FPGA - internal and external (I2C) implementation

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Creating a simple testbench

Programming ICE40 FPGA on a board?

Your choice for <$3 FPGA/CPLD with >50 IO, >200 LUT4?

How often do new series of FPGAs come out (xilinx)

Developer runs Doom on Altera CycloneV

TL866CS on Linux/ WINE