FPGA

Book on SMPTE SDI Protocol?

GOWIN GW1NSR-LV4CQN48P (Tang Nano 4K) - user flash

VHDL add and divide

Simplest / Cheapest FPGA for bulk SPI to USB

Help Reading Flash JTAG Port

5V CPLD?

Xilinx ISE 14.7 - IMPACT is a disaster

Or-ing std_logic_vector of dynamic sizes

newb question

Low-end FPGA selection help

Simulating ISE 14.7 in Modelsim

MGTAVTT and MGTAVCC power supply in Kintex development board

Cyclone IV GX EP4CGX22 LVDS pins

Best and Worst HDL Features

Wrong voltage DDR3 chip on Arty A7 board?

Synchronous FIFO sizing issue

FPGA interface to AT328p debouncing

GOWIN Semi FPGA - BRAM IP usage

Register power consumption on FPGAs

FPGA internal logic analyzer

Quartus 19.1 on Ubuntu 18.04 problems with internet and usbblaster

NEORV32 (RISC-V) soft-core "coremark" result

Soft CPU tools

FPGA with 64 kByte en-bloc RAM?

Gowin AR (GW2AR-LV18QN88C8/I7) dual mode pins!

Vivado/Vitis 2020.2 is out

AMD/Xilinx announced Spartan UltraScale+ family

Help with PS2 keyboard interface?

ICE40 series questions, from a noob

Lattice ICE5LP4K Propagation Delay

Most efficient way of going through a std_logic_vector

Dual port ram with different data widths

Devices containing repurposable FPGAs

Cyclone FPGA question

How to global reset xilink xc2c256 to programable state

Arria 10 FPGA's in china

RISC-V evaluating on FPGA board

Xilinx Programming for xc9536

CYCLONE V HPS - ACCESS SDRAM CONTROLLER SUBSYSTEM OVER JTAG WITH OPENOCD

Soft CPU Design on Zedboard: What will it take to get any embedded os running?