FPGA

Help with PS2 keyboard interface?

NEW PCIe over USB-C Thunderbolt 3/4 interface for SQRL Acorn/Nitefury CLE-215(+)

Lattice ICE40 instantiating RGB/IR pins as regular user IOs.

Xilinx ISE -- Coregen DDR Controller IP problem -- Spartan 3e

generating arbitrary waveforms with zynq 7000 series

VERILOG: Equality test with don't cares

Install Vivado on SD card (use NTFS)

Net "clk50" not found - only after adding extra "process" block (VHDL, Xilinx)

Error 0xc0000142 on Xilinx SDK

Your choice for <$3 FPGA/CPLD with >50 IO, >200 LUT4?

Vivado / Vitis 2022.1 on Ubuntu 22.04 LTS?

Serializing: shift registers vs. multiplexers

(de)Compressing Altera FPGA streams

Altera Quartus II ROM megafunction?

SystemVerilog Example Testbench which Saves a .BMP picture and executes a script

iCE40HX -- can it be clocked from any input pin?

Starting with ICE40, advise on IDEs and environment

[Solved] Cyclone V (de10-nano) SDRAM controller - how to reserve memory for FPGA

VCD file identifier length

How much "Higher level" verilog is used in industry? (Adder example)

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No more Xilinx CPLDs and Spartan 3s

Help required in Library of Zyn 7010 by xilinx SoC

A 5V CPLD in 2023?

Tang Nano 1K (Gowin FPGA) VGA output - artefacts, sync problem

Getting started Altera Flex 10K questions from FPGA newby

Goldschmidt Division

5-stage pipelined CPU and synchronous memory access

MUXes or tristate for busses?

Kintex-7 board - good deal?

Automated tests with Xilinx ISIM on windows

Understanding Skid Buffer Mechanism

Partial reconfiguration of FPGA on the fly

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Jtag with Wiggler

Xilinx clocking wizard - Requested frequency vs actual frequency

TL866CS on Linux/ WINE

EBAZ4205 questions / problem

VHDL add and divide

Reading contents of Altera PLD

Cordic on verilog

Values of signals AT the rising/falling edge