FPGA

RS-232 on ice40 UP5k

RUMOR: Intel looking to buy Altera

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Running DOOM on a tiny ice40

Running Xilinx Vivado HLS from in the Cloud - Can it be done?

S_AXI_AWREADY always red X in Vivado simulator

Sampled AT40K10-2DQU Now What?

Saturating counters

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Schematic for old QMTECH Zynq XC7Z010 Starter Kit

Schematic of the circuit for XILINX XCVU13P VIRTEX.

Screening bad FPGA parts

SD card/SDIO 3.0 level translation solution

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Searching for Launch Diagun firmware from EPM240 Chip.

Searching for Quartus 14.0 installer [solved]

Seeking Book and Library Recommendations for FPGA Networking Projects

Selecting pin impedance on fpga

Selection and general know how of building an Arcade ROM board emulator (FPGA)

Selling Xilinx Spartan 3A Dev Kit

SerDes headache on Xilinx FPGA

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SERDES pronunciation?

Serializing: shift registers vs. multiplexers

set_{input,output}_delay for external bus

set_multicycle_path questions

shocked, how can a 60Mhz pixelclock LCD have 50PIN 24Bits TTL interface?!?

Should a new EPM3064A be 'blank'?

Should i care about AXI4 for my project ?

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Should I use an FPGA for this project?

Should I use one big always block or several smaller ones?

Simple Fade Counter as a tool for get students skills

Simplest / Cheapest FPGA for bulk SPI to USB

Simulate Xilinx libraries on Vivado

Simulating BRAM with lattice/aldec tools

Simulating Gowin IP cores

Simulating ISE 14.7 in Modelsim

Simulating Memory in verilog

simulation in gowin fpga designer

Simulation on Vivado

Simultaneous read/write with Quartus-|| single clock FIFOs

Sine Wave on FPGA

Sipeed Spartan Edge Accelerator Board and HDMI output

Sipeed Tang Nano embedded flash programming