FPGA

Free softcores usage: XILINX x ALTERA

Variable clock divider

ATF1502 programming & 'wrong' id (fake?)

Altera FLEX 8000: Extracting "bitstream" from .sof file?

Intel/Altera brings FPGA to Xeon Broadwell chip

MIPI RX low frequency

Altera Cyclone V SoC FPGA talking to HPS SDRAM

Comparing performance of genuine vs cloned programmers for Intel/Altera FPGAs

How exactly does differential signal lead to low power consumption in FPGAs?

Xilinx's "Device Lookup" Service

USB BLASTER (FTDI245 vs ch552x) Quartus “No Hardware”

Xilinx Announces Vitis

State machine design choice

Are latches always bad?

Verilog: Adding "slices" of numbers

Divide/Mod a 32-bit value by 1000.

Exploring an old FPGA and software (Altera Cyclone with Quartus-II 10.1)

USB3320 Device not able to detect with Zynq RFSoC

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OpenCores.org login

Renesas SLG46826 GreenPAK SPLD, what are the three memory regions used for?

Xilinx project with USB (ULPI PHYs)

Help with Altera Cyclone III configuration problems.

Faster FPGA compilation times using... FPGA? GPU?

DDR3 Refresh and Micron DDR3 model

New generateur DDS with Altera cyclone IV.

FPGA/CPLDs that are hand solderable

NCO to generate square wave

Wrong voltage DDR3 chip on Arty A7 board?

PALCE Chips

Should I use an FPGA for this project?

Quick checking for VHDL syntax

FOR SALE: Altera Terasic DE1 Development Board Kit

#Rant: Intel can't even host files correctly.

Question about MAX7000 CPLDs

Any clue with this HDMI IC Chip is = "TC9138A" (QFN package)?

Power Consumption of Cyclone IV on each voltage rail

Should i care about AXI4 for my project ?

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Xilinx FPGA Drive Strength Explanation

Good books on Computer Architecture and CPU design