FPGA

Xilinx CPLC Programmer

How to set a false path in Vivado using an MMCM or PLL output clock?

Help converting JED to VHDL or ABEL

Help me understand the Gowin speed grade

Xilinx XCZU2EG - Flashing spi flash over jtag?

A question for HDL developers. Where do you place your source and testbenches?

How to convert a 16-bit unsigned to 16-bit signed for multipliers

FPGA & CPLD Marking & Part Number - Replacement

Does XC2C64A CPLD Have Internal Memory For the Storage of the Code?

Kintex Transceiver Init

Efinix FPGA design sometimes a signal is not set high...

[ANNOUNCEMENT] Apio support for Gowin FPGAs is available for testing.

Integrating a Custom DCP into a Vivado Project

VHDL Made Easy (David Pellerin, Douglas Taylor) CD content

Spartan-6 -- safe to provide VCC_AUX and VCC_IO only?

ECP5: Setting Vref off recomended limits. Any experiences?

Advice for my graduation project

How to have a reset signal for a Sipeed/Tang verilog design?

[SOLVED] EPM240 and boundary scan

Reading a 16L8 PAL / question on early SRAM card

problem with AXI bus

ACTEL Activator 2S - APSW software needed

ECP5 SPI flash programming using open source tools

Ise Would not detect XC6SLX45

Anyone using Xilinx XC2k XC3k XC4k FPGAs?

Programming (non-JTAG) MAX7000 devices

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where to get prehistoric SW for earliest (PALCE&GAL) PLDs ?

Mixing verilog and system verilog?

Latest version of Anlogic IDE?

(book) Pipelined Multi-core MIPS, Implementation and Correctness

New TI tiny PLDs (TPLD)

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AGM CPLDs & FPGAs?

XC9500XL : using "Timing driven" macrocells power setting

FPGA beginner: I2C slave

Re-programming Secure Microchip ATF150x series CPLD devices

Salvage board for sale on ebay

Ultrazynq MIO pins and JTAG EXTEST instruction

My first FPGA (MAX10) design : some questions about clock and other aspects

building analog devices ADC HDL examples

Trying to create accelerator with vivado + SDK