FPGA

PS PL Communication using AXI DMA and FreeRTOS on zynq arty z7-20

State machine design choice

Programming (non-JTAG) MAX7000 devices

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Reading the programming of PAL chips

3 bit Dff Counter Issue

A FPGA Audio System in raspberrypi size and open source later.

OpenCores.org login

How to design UART peripherals IP?

FPGA Verilog Project - Saving values for future processing

SD card/SDIO 3.0 level translation solution

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Gowin Vs. Yosys

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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Failed reading data from DDR4

Gowin Simulation

Pruning bits in digital downconverter (DDC)

VHDL CODE QUESTION

Programming with Topjtag trought blacfin only

Is my petalinux image too big?

Xil_Out32 causes my program to crash?

FPGA Bluetooth/WiFi Project

Verilog best way to replicate if else logic inside always block? Macros?

Lattice FPGA programmer

Hyperram to MAX10 (with no DQS shift)

Design cascaded sinc filters, how to?

DDR3L -> DDR3 compatibility

GateMate - An European FPGA

Detection of damaged pins of FPGA - CYCLONE V - 5CSEBA2U23I7SN

$20 FPGA board with 2x8 PCIe and 2x QSFP

AMD/Xilinx announced Spartan UltraScale+ family

MIPI RX low frequency

Can Microchip Configurable Logic Block (CLB) match UART address?

Newbie DRAM interfacing questions

Altera is back

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Problems with Quartus Modelsim simulation

Seeking Book and Library Recommendations for FPGA Networking Projects

Guide: Getting Xilinx ISE to work with Windows 8 / Windows 10 (64-bit)

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Synchronized SPI communication between three FPGAs using VHDL

Bram Memory Size Configuration

OpenHBMC. Open-source AXI4-based HyperBus memory controller

Gating the clock