FPGA

FPGA VGA Controller for 8-bit computer

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Gowin GW1NSR-LV4C - using CM3 with HperRAM ref design

Programming (non-JTAG) MAX7000 devices

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Poor man's FPGA DAC

Fast ADC interface with FPGA

How to read data in Verilog at a particular clock edge?

Reverse engineering Anlogic AL3_10 FPGA

Texas Instruments Bipolar TIBPALs Programming Algorithms

Kria SOM Carrier with Dual FMC?

Using ULPI USB PHYs for custom data links

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Vivado: Synthesis crash (address violation) at "Start Cross Boundary" stage

In Verilog, is it possible to define XXX only if a parameter is set?

A Verilog I2C initializer with integrated RS232 debugger

Need a really dumb PC/Win RS232 terminal program.

Arrow DECA MAX 10 board for $37

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BUFGMUX glitch-free behavior

How to use FIFO to process fast ADC data

Help Please: (Virtual) JTAG Interface - data transmission

WTF Xilinx

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DINI Group DNV7F2A

Verilog Floating Point Clock Divider Release.

Video Upscaling and Overscan

Used Bittware board

Input signal synchronization

Long time since I've played with PLD's.

Gowin M3 CPU usage with FPGA fabric

New FPGAs from Renesas

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Help with converting old PALs to GAL

Any clue with this HDMI IC Chip is = "TC9138A" (QFN package)?

Schematic for old QMTECH Zynq XC7Z010 Starter Kit

New Zynq based SOM

Good intros to FPGAs?

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newb question

SoC as alternative to STM32H7

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Turn off name mangling during Vivado behavioural simulation

Playing with old XC3000A + XACT 5.2.1... no pins assigned or routed

How to download ispVM System software version 17.7 (or later)?

BrianHG_DDR3_CONTROLLER open source DDR3 controller. NEW v1.60.

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Forcing usage of clock enable in MAX7000 CPLDs

Looking for instant on FPGA or CPLD for a current project