FPGA

CPLD passthrough in ISE

Vivado net delay tuning

« 1 2  All »

Vintage Altera

Reasonably priced FPGA dev board that has RF i/o?

ISE v14.7 on Windows10, through VirtualBox emulation

XC6SLX150:: any eval "essential" board?

Advice on an FPGA project

« 1 2  All »

Error In Encoder (Verilog Code)

Long time since I've played with PLD's.

Xilinx CPLC Programmer

Does XC2C64A CPLD Have Internal Memory For the Storage of the Code?

FPGA & CPLD Marking & Part Number - Replacement

Help me choose a starter kit

PMIC for Z7020

Spec-ing ADC to interface with FPGA

113 and increasing weekly blogs on the Xilinx Zynq

VHDL Case Statement

« 1 2 3  All »

iCE40HX4K

where to get prehistoric SW for earliest (PALCE&GAL) PLDs ?

Stupid question - what does axis mean?

Implementing Verilog designs in real hardware

Gating the clock

Derived clocks, best practices?

Critique of first design

Resources for learning FPGA

« 1 2 3  All »

Basys 3 Pmod Tips

Reset in Verilog isn't working as planned

Cyclone III EPC4 flash - programming off board

Small footprints with 'many' min 12G tranceivers

5V CPLD?

Intel to spin off FPGA biz

FPGA SPI Timer, help needed

FPGA text overlay on HDMI - can't meet timing

SerDes headache on Xilinx FPGA

« 1 2  All »

Altera 5M80Z CPLD programs ok but little current draw

Xilinx ISE on Ubuntu

VP1902

Simulating Gowin IP cores

1Gb Ethernet core

« 1 2  All »

2nm Chips