FPGA

Vivado net delay tuning

« 1 2  All »

CPLD passthrough in ISE

Vintage Altera

Reasonably priced FPGA dev board that has RF i/o?

ISE v14.7 on Windows10, through VirtualBox emulation

XC6SLX150:: any eval "essential" board?

Advice on an FPGA project

« 1 2  All »

Error In Encoder (Verilog Code)

Long time since I've played with PLD's.

Help me choose a starter kit

PMIC for Z7020

Spec-ing ADC to interface with FPGA

113 and increasing weekly blogs on the Xilinx Zynq

VHDL Case Statement

« 1 2 3  All »

iCE40HX4K

Implementing Verilog designs in real hardware

Gating the clock

Stupid question - what does axis mean?

Critique of first design

Resources for learning FPGA

« 1 2 3  All »

Derived clocks, best practices?

Reset in Verilog isn't working as planned

Basys 3 Pmod Tips

Cyclone III EPC4 flash - programming off board

5V CPLD?

Intel to spin off FPGA biz

FPGA SPI Timer, help needed

FPGA text overlay on HDMI - can't meet timing

SerDes headache on Xilinx FPGA

« 1 2  All »

Altera 5M80Z CPLD programs ok but little current draw

Xilinx ISE on Ubuntu

ACAP Real prices

Net 'myled' does not have a driver?

Gowin AR (GW2AR-LV18QN88C8/I7) dual mode pins!

Gigabit Ethernet Example code

Xilinx Transceivers

VHDL SPI core

Problem in Generate

Opening Gowin VCD files in Questa sim

Capturing ADC Data using LVDS interface