FPGA

AHB-Lite Crossbar

Determine whether a binary number is of power of two in verilog code

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Elegant way to select output type from a register or wire ?

NoC : Hoplite VS HopliteRT VS HopliteBuf

Terasic FPGA Dev Board - Altera DE2-115 vs SoCKit

Vivado for Windows, what do I need

(de)Compressing Altera FPGA streams

(FS) Xilinx Virtex 5 evaluation board XUPV5 (ML505/ML509)

(Newbie) Xilinx JTAG - Ebay Clone

[Closed:Faulty] Clock works intermittently - Cyclone IV board from Aliexpress

[Constraints 18-5210] No constraints selected for write.

[FPGA] From zero to DVB parsing

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[FS EU] Altera FPGA Board etc

[Lattice Diamond] Which available simulator?

[newbie] Doubt on verilog code

[SOLD] Xilinx FPGA - Spartan 3E Starter Kit (UK)

[SOLVED!] Vivado elaborate fails

[SOLVED] Cyclone III project on Windows 10 with Quartus V13

[Solved] Cyclone V (de10-nano) SDRAM controller - how to reserve memory for FPGA

[SOLVED] JLlink, Quartus, LimeMini SDR: SDR not working after reflashing

[SOLVED] ZynqMP boot Linux from MMC

[Solved]Cannot download Quartus II web edition

[Vivado] Strange timing of the simulation run

[Xilinx SDK] Target reset in debug perspective

[Zynq] transferring data between CPU cores and fabric without too much hassle

"buy cheapest fpga board you can find" - i struggle to find tutorials (ISE)

"Remote Sense Z-Short" on Xilinx AC701

#Rant: Intel can't even host files correctly.

$20 FPGA board with 2x8 PCIe and 2x QSFP

10 level logic in VHDL (for simulation only)

113 and increasing weekly blogs on the Xilinx Zynq

1Gb Ethernet core

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2 Word, first word fall through (FWFT) FIFO, FIFO style elastic buffer for speed

2019, the best way to learn CPU on FPGA

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2nd Order Sigma-Delta Digital to Analogue Converter (SD-DAC) in Verilog

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2nm Chips

4 Layer Board for ZYNQ and DDR3

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48-bit unsigned integer to 32-bit IEEE-754 float for Xilinx 7-series (VHDL)

5 V CPLDs. What's recommended today?

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5-stage pipelined CPU and synchronous memory access