FPGA
Topics
[2] Programming (non-JTAG) MAX7000 devices
[3] Xilinx DDR Controller Strange Behavior in Sim
[5] SD card/SDIO 3.0 level translation solution
[6] I need to get my head around timing (Xilinx)
[7] UART recommendation? Verilog/VHDL, supports 2 stop bits
[9] Calculateing the size of a pipeline vector
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