FPGA
Topics
[1] Verilog best way to replicate if else logic inside always block? Macros?
[2] FPGA Bluetooth/WiFi Project
[4] Hyperram to MAX10 (with no DQS shift)
[5] Design cascaded sinc filters, how to?
[6] Gowin Vs. Yosys
[7] DDR3L -> DDR3 compatibility
[8] GateMate - An European FPGA
[9] Detection of damaged pins of FPGA - CYCLONE V - 5CSEBA2U23I7SN
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