FPGA
Topics
[1] XC9500XL : using "Timing driven" macrocells power setting
[2] Pull-up/pull-down resistors
[3] Multiple MIG controllers clocking
[4] SD card/SDIO 3.0 level translation solution
[6] UART recommendation? Verilog/VHDL, supports 2 stop bits
[7] Flash backed LLMs on FPGA?
[8] Programming (non-JTAG) MAX7000 devices
[9] Xilinx DDR Controller Strange Behavior in Sim
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