FPGA

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[1] SD card/SDIO 3.0 level translation solution

[2] I need to get my head around timing (Xilinx)

[3] UART recommendation? Verilog/VHDL, supports 2 stop bits

[4] Maximum utilisation

[5] Calculateing the size of a pipeline vector

[6] Programming (non-JTAG) MAX7000 devices

[7] The Blair Witch story of my first FPGA devboard made from a printer front panel

[8] IC configuration approach - Hardware vs. software

[9] Vcd Viewer (VcdView) upgrade available (now with equations)

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