Electronics > FPGA
A question for HDL developers. Where do you place your source and testbenches?
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zapta:
A question for HDL developers. Let's say that you have a verilog file named my_module.v and a testbench for it called my_module_tb.v.
1. Do you place both files in the same directory or in separate directories?
2. If you answered 'seperate directories', is the testbench directory under the source directory or do you use two independent directories trees, one source source files and one for test files?
AK6DN:
I use multiple directories to keep files.
Under my PROJECT directory, I typically have SRC and TESTBENCH directories, with project specific source and testbench files in each.
I also have LIBRARY SRC and TESTBENCH directories, where the files are shared across multiple projects.
pcprogrammer:
Just as for software development it does not matter from the computer perspective.
For the developer and coworkers (company) it is good to have a fixed structure across work. So using a similar directory structure for all your projects is good sense.
A lot of the proprietary IDE's for FPGA development force some directory setup upon you for their IP (intellectual property) stuff, and can write a load of work files to the top directory cluttering the perspective. So having a dedicated source directory within the project directory makes it easier to keep the important stuff separated from the less important stuff.
gael:
In our practice, everything in VHDL/Verilog is sources, under some common root tree, and we put the synth intended ones under <root>/synth and the sim intended ones under <root>/sim.
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