ABEL to VHLD conversion

[Ribster]

Hi all,

I have a design that needs to be ported to a modern FPGA.
The hardware design is done and i can program the new FPGA.
The old code however is written in ABEL and used ispLever.
With some research i'm feeling that ABEL to VHDL conversion is not quite possible through a conversion tool ?

Anyone has got any experience on the lattice platform of converting this ?

Kind regards

[SiliconWizard]

Typical stuff written in ABEL was rarely very big. Shouldn't take a lot of time translating this manually, even if just using low-level constructs in VHDL. So how large could have your code been?

[Bassman59]

Do it by hand.

And remember that VHDL has many constructs that ABEL didn't, for example numbers for counters and the like. Your translated code will likely be simpler and easier to understand!

[nctnico]

Do it by hand.

And remember that VHDL has many constructs that ABEL didn't, for example numbers for counters and the like. Your translated code will likely be simpler and easier to understand!

But it will have to be re-validated (tested) from A to Z.

[Bassman59]

Do it by hand.

And remember that VHDL has many constructs that ABEL didn't, for example numbers for counters and the like. Your translated code will likely be simpler and easier to understand!

But it will have to be re-validated (tested) from A to Z.

You have to do that with an automated conversion too.