Hi,
I am playing with a Xilinx XC9500XL CPLD.
My design is basically a bridge between a "high" speed and a low speed parallel bus, and some control logic.
Since it is getting quite warm I am experimenting with the macrocell power setting.
Setting the global power flag to low makes this design not work, I guess because of the high speed side timings.
I am now trying to use the "Timing driven" setting in the Fitting properties, in order to set the macrocells to low power on the low speed side only.
Setting constraints on the clocks made the fitter to set a couple of internal signals to low power, but everything else remained "standard" power. Constraining slow timings on periods and offsets does not seem to change the power of most macrocells.
I have the CPLD timing xapp1047 and the Xilinx Constraints Guide ug625. I found
https://adaptivesupport.amd.com/s/article/2717?language=en_US but the said "Xilinx Answer 2146 is not available anymore" (and the URL was not indexed in the wayback machine). Yet I could not find a solution, neither a good example on the net.
By chance do you have a clue about this "Timing driven" power setting ?