Author Topic: XC9500XL : using "Timing driven" macrocells power setting  (Read 5275 times)

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Offline SassaTopic starter

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XC9500XL : using "Timing driven" macrocells power setting
« on: September 25, 2024, 07:56:37 pm »
Hi,
I am playing with a Xilinx XC9500XL CPLD.
My design is basically a bridge between a "high" speed and a low speed parallel bus, and some control logic.

Since it is getting quite warm I am experimenting with the macrocell power setting.
Setting the global power flag to low makes this design not work, I guess because of the high speed side timings.

I am now trying to use the "Timing driven" setting in the Fitting properties, in order to set the macrocells to low power on the low speed side only.
Setting constraints on the clocks made the fitter to set a couple of internal signals to low power, but everything else remained "standard" power. Constraining slow timings on periods and offsets does not seem to change the power of most macrocells.

I have the CPLD timing xapp1047 and the Xilinx Constraints Guide ug625. I found https://adaptivesupport.amd.com/s/article/2717?language=en_US but the said "Xilinx Answer 2146 is not available anymore" (and the URL was not indexed in the wayback machine). Yet I could not find a solution, neither a good example on the net.

By chance do you have a clue about this "Timing driven" power setting ?
 

Offline JimboJack

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  • Country: au
Re: XC9500XL : using "Timing driven" macrocells power setting
« Reply #1 on: November 21, 2024, 02:22:30 am »

9371 has alternative but similar info, which by looks like it line (1) is already have tested.

9371 - CPLD XC9500 Family - Suggestions for lowering power consumption
https://adaptivesupport.amd.com/s/article/9371?language=en_US

Solution
1. Set the device to Low Power mode. This is done by setting the macrocell power setting to "Low" in the implementation options.
2. Use global resources instead of product terms whenever possible
3. Set the unused I/O to ground. You can accomplish this by setting "Create Programmable Ground Pins on Unused I/O" in the implementation options.
4. For XC9500 5-volt devices, ensure that you have pin and local feedback enabled in the implementation options.

Understanding XC9500XL CPLD Power  Xapp114.pdf
https://docs.amd.com/v/u/en-US/xapp114

Using the XC9500XL Timing Mode Xapp111.pdf
https://docs.amd.com/v/u/en-US/xapp111
 

Offline SassaTopic starter

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  • Posts: 8
Re: XC9500XL : using "Timing driven" macrocells power setting
« Reply #2 on: December 07, 2024, 04:28:38 pm »
Hi.
The manual way I found to do it is to add the PWR_MODE attribute before each output, inout and reg declaration inside my verilog code.
Code: [Select]
(* PWR_MODE = "LOW" *) reg myreg=1'b0;
 


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