Author Topic: AGM CPLDs & FPGAs?  (Read 3067 times)

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Offline ResistorsAreFutileTopic starter

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AGM CPLDs & FPGAs?
« on: November 25, 2024, 12:50:59 pm »
I'm having to transition many of my designs away from Xilinx XC9500XL CPLDs as those parts are EOL, and also settle on an FPGA family for more ambitious future projects. Ideally I'd like to use the same tools for both, so Altera's Max V and Max 10 parts have been the front runners despite the cost of the Max 10 and larger Max V parts being quite a lot higher than I would like.

Then I found the AGM parts, which seem to be clones of the Max II, Max V and Cyclone IV. Their prices are impressive, less than $3 for a 10K LE FPGA in a QFP-144 package and their 2K CPLDs are an order of magnitude cheaper than the Altera parts.

Does anyone have any real world experience with these things?
 

Offline up8051

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Re: AGM CPLDs & FPGAs?
« Reply #1 on: November 30, 2024, 10:12:37 pm »
Did you somehow manage to download the "Supra" program?
 

Offline JimboJack

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Re: AGM CPLDs & FPGAs?
« Reply #2 on: November 30, 2024, 11:58:46 pm »
I found it from different sources and not using that chinese backdoor malware app.

they seem to have two website
http://www.agmsemi.com/  has all the information
http://www.agm-micro.com/

do a web search on these file names

Supra-2023.11.b0-84524805-win32-all
Supra-2023.11.b0-84524805-win64-all
agRV_Pio-1.6.6-win64

agRV is their latest release superseds supra-2023 i installed both to see any difference could not find any however the supra zips contains the license file.


1. from my take it can only do verilog, no VHDL support, uses YOLO I think with their GUI and scripts on top.
2. agRV release complains on the install , you need to manual install platform.io with the correct paths you see it in the install windows

look for AGMPILL on search engine it point to a github with example files, which has the designs they sell on aliexpress, it does something no way to test the output it created yet.


hope it helps, as always be safe use VM's :)
« Last Edit: December 01, 2024, 12:02:37 am by JimboJack »
 

Offline ResistorsAreFutileTopic starter

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Re: AGM CPLDs & FPGAs?
« Reply #3 on: December 05, 2024, 03:57:21 pm »
Thanks for the advice.

I've got Supra installed in a VM and it recognises the attached Altera USB blaster and can read the chip ID from a Cyclone IV, so the programming part at least seems to be working. No idea what I'm doing with the Quartus project migration part of Supra yet, the 'manual' is not informative even when translated from Chinese  ;D

Looks like I will be working up a break-out PCB for the AGM16K and possibly the AGRV2K as well.



 

Offline JimboJack

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Re: AGM CPLDs & FPGAs?
« Reply #4 on: December 06, 2024, 01:02:27 am »
can you tell me please how it goes :)
I want to try the AGRV2K  CPLD replacement.

From the datasheet pretty weak,  could not see what the max clk rate  or the max Mhz on the I/O pins it can do.


 

Offline monk88

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Re: AGM CPLDs & FPGAs?
« Reply #5 on: December 10, 2024, 11:21:58 pm »
Alright, Greetings everyone!

I've made this account to comment on the AGM FPGAs and my experience with them so far. I am trying to find cheaper "alternatives" to Altera's devices, and AGM came right in time.
I've bought two boards from Aliexpress:
- AGM TCX (black) board with AG10KL144H FPGA
- Etree F01 again featuring the AG10KL144H  FPGA " alt="" class="bbc_img" />

The Supra SW you can download from here: https://t.me/agmfpgadoc/142

Anyway, I will be short as it is very late here. I managed to run several examples on the AGM TCX board, specifically targetting the NIOSII Soft CPU with some periphery. I was able to create and run an SOPC system, toggling some leds (PIO) and trying to print some text message (via JTAG-UART).
Now, the NIOS CPU and its application ran fine, except that the printed message over JTAG was not visible. The problem is that JUART-Terminal application, running on the PC, would not attach/find the JTAG periphery of the FPGA. Also, because of that I guess, it is not possible to use the debug (to downlaod and debug from the NIOSII SBT Eclipse IDE) your firmware on the SOPC HW (.sof) that you may have already programmed to the FPGA. So the JTAG-UART and JTAG debugging are broken with AGM FPGAs , and not usable.

I am attaching pics and an example project I had used if anyone wants to check for themsevles.
https://drive.google.com/file/d/1Qft_PTqO6CI-o_n6OHdiBJCy_upovUHZ/view?usp=sharing
 

Offline JimboJack

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Re: AGM CPLDs & FPGAs?
« Reply #6 on: December 12, 2024, 01:08:26 am »
« Last Edit: December 12, 2024, 01:21:15 am by JimboJack »
 


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