First question would be: have you looked at existing alternative HDLs, such as - as you mentioned - SpinalHDL, nMigen, Chisel, ...?
I've looked at nMigen to some degree, however the documentation is rather limited at this phase so the learning curve feels pretty steep.
What do you think you could do better or at least differently, apart from using Racket? Also what's your rationale for using Racket here?
One advantage of nMigen is that it is embedded into Python, so that in addition to describing hardware with the nMigen libraries, you can make use of the rest of Python to allow for more automation and generation of your HDL. A really trivial example would be calculating filter coefficients and then inserting them into the design. Unfortunately the syntax nMigen uses for describing hardware is pretty awkward because it has to conform to Python's syntax. Racket allows you to extend its syntax pretty easily, and so I think it would be possible to create a really clean embedded HDL. The advantages would be having an elegant syntax for the HDL, while still having access to Racket as full featured programming language for automation and generation.
I understand that your topic is to help you answer at least the two first questions, but IMHO, if you're not skilled enough in existing HDLs to be able to answer this yourself, designing a new HDL might be a tricky endeavour. Now getting feedback from others is always good, but I think that would have helped if you had started by exposing what you intended on implementing and why.
I agree with you. For Verilog, some of the things that annoy me about its syntax is that you can't write to the same register in different always blocks, even if the logic is designed so that there will never be an issue with multiple drivers to a single register. For example:
// let cond_a and cond_b be mutually exclusive events
// we may write write:
always @(posedge clk) begin
if(cond_a) begin
foo <= 2'b1;
end
else(cond_b) begin
foo <= 2'b3;
end
end
// but if cond_a and cond_b are generated by fairly unrelated portions of the design
// it might be nice to have separate always blocks in different parts of the code to
// write to foo. For example:
always @(posedge clk) begin
if(cond_a) begin
foo <= 2'b1;
end
// some more stuff here
end
// lots more stuff here
always @(posedge clk) begin
if(cond_b) begin
foo <= 2'b3;
end
// some more stuff here
end
// while in some cases this might be a lot more clear and readable,
// it is illegal in Verilog
Another feature I think might be really nice in Verilog, is a way to group a set of signals together and refer to them as a single bus. There are certainly ways to do this quickly, but it might be nice to have something like the record type that VHDL has.
I certainly don't know enough about other HDLs to actually attempt to write one yet, but I was hoping that some people would point out things they liked in various languages, so I could go investigate them and learn about useful features/idioms.
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