Power dissipation calculation for FPGA-ADC interface

[matrixofdynamism]

An FPGA can be interfaced with an ADC using CMOS or LVDS. Is there a way to use simulation to predict the power dissipation of the I/O blocks for a given operating frequency for this interface? If so, how can this be carried out?

Here we have an Intel MAX 10 and a Microsemi IGLOO2 being linked to a TI ADC. It would be great to be able to get a very reliable estimate for power dissipation between these two FPGAs when using LVDS and also when using CMOS, to interface with the TI ADC.
 

[matrixofdynamism]

It seems that no one knows the answer to this question after all.

[ejeffrey]

It's not 100% clear what you mean.

LVDS transmitters have a static current draw of 3.5 mA/LVDS pair from whatever supply rail is supplying the IO power.  This doesn't capture dynamic power consumption of the transmitter or consumption of the receivers input amplifier or consumption of the logic connected to it.  CMOS of course doesn't have static power consumption, but for an ADC where the data is changing all the time the dynamic consumption will still be an issue.  The ADC datasheet should give some power numbers.

FPGA development environments have power estimators that tell you for your particular design how much power it will consume.  Be warned, this is a GIGO situation.  The analysis tool will make some default assumptions about how often each pin and flip-flop will change state, if that is wrong the results may not be sensible.

[radiolistener]

but for an ADC where the data is changing all the time the dynamic consumption will still be an issue

it looks that you have experience with ADC+FPGA project, can you suggest some good NCO implementation for digital down conversion working at 100-200 MHz and good spurious performance?

Currently I'm using this cordic implementation, but I can see a lot of spurs, some of them up to -90 dB. I want to eliminate all NCO spurs up to 140 dB dynamic range.

[asmi]

FPGA development environments have power estimators that tell you for your particular design how much power it will consume.  Be warned, this is a GIGO situation.  The analysis tool will make some default assumptions about how often each pin and flip-flop will change state, if that is wrong the results may not be sensible.

Yea, I didn't have a lot of luck using these tools, but it may very well be that I didn't provide good enough inputs, and as you say, the results are only as good as the data you provide.
So the way I typically approach this is as follows - I use XPE (Xilinx Power Estimator) spreadsheet to figure out worst-case current consumption by setting artificially high utilization and switching frequency, then I design my board to this spec, but include hardware for current measurement. Once design is completed and verified in hardware, I measure actual current consumption in the worst possible regime (high die temperature, maximum allowed Vccint voltage), add a safety factor of 1.2 to 1.5 (depending on expected operational conditions) and change PDS to this specs.
But more often then not, I just leave things as they are for the worst-case. Because FPGA typically cost so much more than everything else on a board combined, that it makes little sense to spend additional time resizing PDS, because the savings might not be worth the effort. Exception to this is the case when DC-DC converter I use is a part of pin-compatible family with different current capability, as downsizing PDS in this case involves just loading another member of that family with lower current capability.

[SiliconWizard]

Datasheets usually give you power estimates for IOs. So I'd look that up first to get an idea.

Then yes, some vendors also have power estimation tools, Lattice and Xilinx certainly do, but I don't know about Intel (/altera) and Microsemi.

And that said, nothing will really beat a real-life measurement.

[ejeffrey]

but for an ADC where the data is changing all the time the dynamic consumption will still be an issue

it looks that you have experience with ADC+FPGA project, can you suggest some good NCO implementation for digital down conversion working at 100-200 MHz and good spurious performance?

Currently I'm using this cordic implementation, but I can see a lot of spurs, some of them up to -90 dB. I want to eliminate all NCO spurs up to 140 dB dynamic range.

I don't have any implementation I can point you at.  It shouldn't be a problem to get 140 dB spur range out of an NCO as long as you throw enough precision at it, I'd play around with this in matlab or python just to make sure your expectations right.  Of course spurs in the NCO are one thing but clock jitter and ADC non-linearity will degrade your SFDR well below 140 dB.

[hamster_nz]

What are the input and output widths of your CORDIC module?

It is pretty much only limited by how much FPGA resources you wish to throw at it, and the latency you require.