Altera / Intel Arria 10 clk, PLL input pin

[Wiljan]

I got hold on a board with Altera/Intel Arria 10 FPGA 10AX115H4F34

There is a 100Mhz connected on PIN_AK16 and I have some LED's as well

I use Quartus II 15.0 and program it via JTAG

If I take the AK_16 and send it to a counter and the to the LED's the and divide by 24 they are flashing nicely so far so good.

So next I want to do is to have a PLL so I can have other freq than the 100Mhz.
On other Altera FPGA's it's just to add in a ALTPLL and set the numbers of outputs you need and the freq.

Here on the Arria 10 it's called IOPLL and I do the same with the output I need (I want to have a higher clk for main core and a lower for some uart.

So when I define the AK_16 (the 100Mhz) in the pinplanner to be my input for the IOPLL  refclk in and compile I get this error:

Error (14566): Could not place 1 periphery component(s) due to conflicts with existing constraints (1 pin(s))
   Error (175020): Illegal constraint of pin to the region (78, 6) to (78, 9): no valid locations in region
      Info (14596): Information about the failing component(s):
         Info (175028): The pin name(s): Ext_PLL_ref
      Info (175015): The I/O pad Ext_PLL_ref is constrained to the location PIN_AK16 due to: User Location Constraints (PIN_AK16)
         Info (14709): The constrained I/O pad is contained within this pin

What do I miss here?

Is it only some pin's which can be used as input t IOPLL?
What pin number/name should I look for to have the input for the IOPLL to be happy?

There are other clk's 25Mhz connected as well but they look's like they are for different purpose

[radiolistener]

Is it only some pin's which can be used as input t IOPLL?
What pin number/name should I look for to have the input for the IOPLL to be happy?

Yes, PLL can be feed from CLK pins only. This is because there is no internal route between PLL input and regular pin.

So, this is impossible to feed PLL with a signal connected to a regular pin. You're needs to use CLK pin only for the clock.

CLK pins provide better jitter performance and you can use PLL for precise phase shifting. If you use regular pin, you cannot do that.

You can find which pins are CLK compatible for your FPGA chip in the pin planner. See menu Assignment=>Pin Planner.

Usually Altera FPGA consists several PLL. In order to reduce clock delay these PLL are physically located at opposite sides of the FPGA chip. And CLK pins are placed near PLL module to reduce clock delay and jitter.

For example, there are 4 PLL at 4 corners on my FPGA chip. And you can see it's CLK pins are placed at opposite sides of the chip. They are physically placed near the PLL which will be used if you route it to feed PLL module.

As you can see, there may be a trouble if you want to feed several CLK pins from opposite chip side to the single PLL. Because one of CLK pin will have too long route path.

Also it means that you need to feed CLK pin directly to the PLL. But you can also use PLL output to feed another PLL.

[asmi]

For Xilinx FPGAs it's possible to use non-clock-capable pins for clocks, but it's highly discouraged because the performance is going to suffer a lot, which is why you will have to add explicit constraint to allow this - by default P&R will fail. This is "the tool of the last hope" if you screwed up your PCB pinout, but still need to do some HW testing until a new revision is ready.

[FenTiger]

if you screwed up your PCB pinout

...or if the vendor screwed it up for you (mumble, QMTech, mumble).

[Wiljan]

Thank you for you input's

I did try a lot of different combination fPLL / IOPLL and for sure they do use different input banks and allocated pins

I found that the board does have a few LOOP's  in/out where the just goes out on 1 pin and then in again on the pin next to it.

I also tried to compile with out any pin defined and the you will see the  the fitter actual have assigned a pin in the block with the PLL

I could take my in clk and then send it out via a LOOP and back in and then to the PLL and it did compile, but did not work ... until I forced the clk via Global buffer.

So I think the Global buffer somehow force to use the clk routing which are separated from normal routing, so now I don't use the LOOP.

The Compilation Report says the are 179 PLL in the chips (I only use 1 )

At least it does work now :-)

[radiolistener]

At least it does work now :-)

if it works in certain cases, it doesn't means that it will work at any condition and don't suffers from timing issues.