Altera Cyclone V SoC FPGA talking to HPS SDRAM

[macgeorge]

Coming from the world of microcontrollers, I have recently purchased a Terasic De0 Nano SoC FPGA board and currently testing small projects focusing on the FPGA fabric of the chip.

While trying to build a VGA controller, I used an "On-Chip Memory" component to store pixel data at the beginning. However, as the FPGA memory space is not enough to hold a frame for a common VGA resolution, the external SDRAM needs to be used. For the De0 nano SoC board, the SDRAM chips are connected to the HPS portion of the chip, so a bridge between the FPGA fabric and the HPS needs to be implemented.

I am not interested (at the moment) into having a memory space which will be transparent to HPS as well, so as a first step, I limited the SDRAM used by the HPS (which boots into Linux from an SD card) from 1GB to 768MB.
To do this, while in uboot, the following commands need to be entered:

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setenv mmcboot "setenv bootargs console=ttyS0,115200 root=${mmcroot} rw rootwait mem=768M;bootz ${loadaddr} - ${fdtaddr}"
saveenvIf for any reason you need to go back to the default setup then the following commends need to be entered:

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env default -a
saveenvIt was interesting to see that if I reduced the SDRAM to 512MB, then Linux could not start (error while booting), I don't know if anyone else can confirm this behavior.

So, if I understand correctly, there are now 256MB for the FPGA to play with, which will not interfere with the hard processor.

The Golden Hardware Reference Design (GHRD) project, provided as an example in the documentation includes all the settings for the setup of the HPS in QSYS and the port mapping of all the pins.

However, even if the SDRAM timings are set on the GHRD, an FPGA-to-HPS SDRAM interface is not setup. Moreover, this interface can be either Avalon or AXI based.

So my questions are:
1) Is there any example project which implements the complete bridge from the FPGA to the SDRAM controller?
2) Would an Avalon type SDRAM interface be more preferable, so as to resemble to the On-chip memory component, which is fairly straight forward to implement?
3) What components need to be added in QSYS to complete the connection?

Thanks in advance!

[Berni]

The whole bridge thing is pretty picky.

The memory controller has to be configured to open its channel to the FPGA and the FPGA design needs to have the HPS block put in to Qsys.

If something is not set up properly it tends to lock up when you try to use it. Such as the Avalon bus being ethernally busy or whatever tried to issue a read on the HPS side getting in to an ethernal wait.

I have a thread on the Altera forums that explains the basics of the bridges and how to make them work in bare metal C