Altera EPM3032 CPLD Guide Tour Please.

[Mechatrommer]

today i received a bunch of components that i ordered. included is 1 piece of Altera EPM3032 as pictured. The reason i bought it because
1) i want to learn a new thing and embrace CPLD and FPGA.
2) since the seller sell this, i grab one just to distribute the shipping cost (lesser for each item) beside the other main components that intended to buy.

but the truth is, i have zero knowledge on this, no programmer no software no nothing, except this single chip. last time i google to find how to program this thing, i dont have a clear direction. iirc there is a device called fireblaster to program it. and about the software, i have no clue. please guide me on where to find the IDE, programmer, guides, notes, pdfs etc. i hope i can build a diy programmer for it instead of having to order from other place. thanx.

[deephaven]

That is opening quite a big can of worms   

If you go on to the Altera website you will be able to find data sheets for the chip. These will also tell you what options you have for programming it.

The software you need to run is available free of charge from their website, it is called Quatus. Be advised that it is BIG - several Gigabytes!

The software will allow you to enter a circuit design in various ways including VHDL and Block definition. The advantage of the latter is that you can enter the circuit as though it was made from individual chips, you can add familiar looking gates, counters, adders etc. If you're mind is more 'software' inclined then VHDL might suite you better as it is a bit like software!

You can program the chip using Altera's Byteblaster (parallel port interface) or USB Blaster (USB port interface). You can get second sourced versions of these which are cheaper. Alternatively you could make your own JTAG programmer, but this will be a lot of work to work out the file format it needs. Maybe someone has done this already?

I think Altera chips are great and most of my designs use various sizes of them. The one you have is very small, but they can get very big AND eye-wateringly expensive for the high-end ones!

[Mechatrommer]

right! i downloaded the 700++ MB file just to find out its the service pack that the other main installer/program need to be installed, what a waste of BW. i think i should downloaded the "web edition" but it doesnt sound good to me... "web"? dependency? so before i download the 2-8 GB file https://www.altera.com/download/software/quartus-ii-we i need to ask, which one? Quartus II Web Edition V11 2.7GB or ACDS v11.0 Windows DVD (ISO) 5.9GB. what the difference of the two? this will be a hell! of downloading!

[deephaven]

I would actually recommend gettting V9.1 Web Edition. I am trying to find the link to where you can download that from and I'll get back to you with it.

The reason for suggesting that version is it's the version I currently use and it is the last one to use 'Classic' timing analysis. This is very easy to use and means you can verify your design by simulating it. On later versions they use a new timing analysis system which is harder work to use.

[deephaven]

OK, I would suggest downloading this 1.7 GB (!) file

ftp://ftp.altera.com/outgoing/release/91sp1_quartus_windows.exe

or go to the directory ftp://ftp.altera.com/outgoing/release/ and click on the appropriate link.

The connection is usually slow so you have to be a bit patient.

[Mechatrommer]

OK, I would suggest downloading this 1.7 GB (!) file
ftp://ftp.altera.com/outgoing/release/91sp1_quartus_windows.exe
or go to the directory ftp://ftp.altera.com/outgoing/release/ and click on the appropriate link.
The connection is usually slow so you have to be a bit patient.

thanx for the link deephaven. looking at the naming convention, i think the 91sp1 is another service pack upgrade, i think the main software is 91_quartus_free.exe (1.5GB) or 91_quartus_windows.exe (2.9GB) still confused with the naming.

since i've downloaded the 10.1sp1, to avoid wasting the bytes, how about downloading the 10.1_quartus_windows.exe (1.3GB)? (or 10.1_quartus_free_windows.exe 3.2GB? damned confusing! free version is alot bigger than normal version 10.1_quartus_windows.exe!) maybe i can get away with new timing analysis, i dont know, who knows? since i never get the feeling of it. i dont even know what timing analysis is, nvm, i'll figure it out.

[joelby]

Don't worry about the 'Web' name - this just mean that it's the free edition (see also Xilinx Webpack). I have a suspicion that they were named during the 'Web' craze about ten years ago and haven't managed to shake it. It has nothing to do with the Web.

[deephaven]

OK, I would suggest downloading this 1.7 GB (!) file
ftp://ftp.altera.com/outgoing/release/91sp1_quartus_windows.exe
or go to the directory ftp://ftp.altera.com/outgoing/release/ and click on the appropriate link.
The connection is usually slow so you have to be a bit patient.

thanx for the link deephaven. looking at the naming convention, i think the 91sp1 is another service pack upgrade, i think the main software is 91_quartus_free.exe (1.5GB) or 91_quartus_windows.exe (2.9GB) still confused with the naming.

since i've downloaded the 10.1sp1, to avoid wasting the bytes, how about downloading the 10.1_quartus_windows.exe (1.3GB)? (or 10.1_quartus_free_windows.exe 3.2GB? damned confusing! free version is alot bigger than normal version 10.1_quartus_windows.exe!) maybe i can get away with new timing analysis, i dont know, who knows? since i never get the feeling of it. i dont even know what timing analysis is, nvm, i'll figure it out.

I can't say with 100% certainty which is the file containing the full install but logically I would guess it's the biggest! As I said before 9.1 gives you a very easy to use waveform editor and it also means it would be easy for me to send you an example project to get going. . If you to decidedto run with V10.1 you could still use my example but it would update the files to be compatible with V10.1.

[joelby]

It seems a bit like the world has moved away from waveform editors and on to pure HDL test benches - for moderately complicated designs, this is a very good thing!

[Mechatrommer]

its because i've downloaded 10.1 sp1 earlier, so i guess i would like to continue and try ver10.1... i believe the project should be cross-version. downloading 10.1_quartus_windows.exe (1.3GB) from last night, about 12 hours already, 56% completion, running at 25KBps. i got warning i'm reaching my bw limit before thing going very slow (5-10KBps). hope for the best, the clock is ticking

[deephaven]

It seems a bit like the world has moved away from waveform editors and on to pure HDL test benches - for moderately complicated designs, this is a very good thing!

I don't usually try to simulate the whole project. If there is a tricky section, I will make a new project of that and get it debugged.

[Mechatrommer]

hi again. i've found a cheap study kit for my cpld.... i think. its within my budget, but i have to make sure i dont get the wrong item. what i need is only capable to program the cpld (epm3032) from pc. the 1st one (item #1) included all the byte blaster "dongle", study/dev kit and 1 more extra altera cpld. the item #2 is the byte blaster alone, but i've seen it before somewhere. i prefer #1 since its all in one, but the funny thing is its cheaper than #2 which is programmer alone. i hope any suggestions from members here. thanx.

Ebay Item #1: Altera CPLD Develope Studying Tool + Atmel ISP download


Ebay Item #2: Altera USB Blaster FPGA CPLD fully Compatable download

[Neganur]

The programmer of the first link seems to be RS232 while the other is USB.
I don't know anything about either of these so I can't recommend anything. I prefer USB programmers though since I always encounter trouble with Windows and the old serial port type programmers.

[mkissin]

If you were considering buying a standalone USB byteblaster, don't get one off of ebay. For the same cost you could get the proper Terasic one, -> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=&No=46

Also, if you wanted to play with CPLDs rather than FPGAs, I'd consider the Terasic Max II Micro kit. It comes with a lot of tutorial information, and has the programmer built in (plus, you can actually use it as a standalone USB Blaster) -> http://www.terasic.com.tw/cgi-bin/page/archive.pl?Language=English&CategoryNo=64&No=215

[Mechatrommer]

that terasic site, is damned slow from here, i'll try later.

[A-sic Enginerd]

Just my $0.02,

since it appears you really don't know what you have, and are running into questions and issues with what's the best way to program it, etc. I would advise pulling down the datasheet for the part and learn about it first. Even that may be complicated. It's been a while since I've dealt with Altera parts, but used to be if you wanted a good rundown of the architecture of the "family" there was a book / datasheet that gave the overall picture. Then for the specific parts there was a separate datasheet, but this time it focused just on what made that part unique in the family. (things like pin counts, I/O types, cell counts, etc.).

Then once you understand just what you have in your hand, that might help you resolve what and how to get the tools you need to work with the part.

On deephaven's comment about VHDL (or Verilog, etc.) being more like software. Eeeeek! That's when people like me always cringe. Yes it is like software in syntax. But that's where it needs to end. A lot of newbies get themselves into trouble when they start writing RTL code with a software mindset then don't understand when it doesn't work the way they want, and that's IF it synthesizes. Please, save yourself much grief and always be thinking in terms of hardware even though you might have something on the screen that looks like software.

[Mechatrommer]

thanx a-sic for the advice. the datasheet has been a good bedtime story for me, i read about the macrocells etc but still have no clue on how to program that, maybe i should work harder next time. i just try to shot blind here with hope that by learning this small cpld, i'll get better picture of what and how this thing work. yes i read its not as simple as a procedural software programming, i imagine its more like brain's neurons working together to get the output simultaneously, thats the interesting subject i'm looking forward to investigate. and i believe i should start small with this 44 pins (just few macrocells) cpld, and its just happen i bought it from a seller which i bought other stuffs from. i need a direction, and this seller gave me one , simply put, i just dont know whats going to happen. just give it a try who knows the luck is on my side.

[joelby]

I personally think it's a bit difficult to fully comprehend macrocells, LUTs, slices, and everything else without having an understanding and some experience of what you'd actually use a CPLD for. Buy a well-supported CPLD development board that comes with an introductory tutorial (flashing LEDs, etc.), which will help you to start to learn the tools and workflow. Then you can start following more generic HDL guides.

Once you're getting dangerous with HDL, it's time to start learning how the device is constructed so that you can optimise your design for the architecture, if you need to.

[A-sic Enginerd]

Once you're getting dangerous with HDL, it's time to start learning how the device is constructed so that you can optimise your design for the architecture, if you need to.

yep, like - avoid latches.
That was a brutally hard learned lesson during the one lab project in college. Still have nightmares about that one. 

[Mechatrommer]

Once you're getting dangerous with HDL, it's time to start learning how the device is constructed so that you can optimise your design for the architecture, if you need to.

yep, like - avoid latches.
That was a brutally hard learned lesson during the one lab project in college. Still have nightmares about that one. 

i will be looking forward to it! could be enjoyable! i get used to that kind of experience anything hard learned will be hard sticked in our brain.

[jahonen]

Another thing to avoid is using of unsynchronized signals in synchronous logic, it can create bizarre behavior (metastable events) of your carefully designed logic and drive you crazy. You have been warned

That means if you have something like a state machine in your design, and you want to bring external inputs from outside to your system, then you must first synchronize these inputs using the clock which runs your state machine. In practice, this is just 2-3 DFFs in series before feeding the signal into the state machine. But it still is easy to forgot.

I have been designing with VHDL and FPGAs for some time now, and I still seem to struggle sometimes with this.

Regards,
Janne

[Rufus]

Another thing to avoid is using of unsynchronized signals in synchronous logic, it can create bizarre behavior (metastable events) of your carefully designed logic and drive you crazy. You have been warned

Depends on the circuit but the chances of you experiencing a metastable state that makes a difference are very low, likely thousands if not millions of times less likely than experiencing a race condition on unsynchronized signals.

[jahonen]

Another thing to avoid is using of unsynchronized signals in synchronous logic, it can create bizarre behavior (metastable events) of your carefully designed logic and drive you crazy. You have been warned

Depends on the circuit but the chances of you experiencing a metastable state that makes a difference are very low, likely thousands if not millions of times less likely than experiencing a race condition on unsynchronized signals.

Yes, I actually meant something like that, but wrote only the metastable for some reason, whereas timing violation would have been more generic term. Usually the effect is in complex circuit that if a 0->1 transitioning unsynchronized signal is used in clocked registers is that part of the registers will register '0' on transition (new value not registered), some will register '1' and perhaps some will experience a metastable state.

Finally in case someone wonders, in contrast to a MCU this is not relevant issue with MCU since all asynchronous ports should be properly synchronized by the chip designer. With digital logic, it is important thing. So bottom line is that one should obey the setup and hold timing requirements, and all will be fine

Regards,
Janne

[A-sic Enginerd]

Some years ago I attended a trade show. IVF maybe? Anyway, took a little seminar on how to optimize designs for FPGA's. They gave a list of the Ten Commandments for digital designers. I'll have to see if I can find that. It's all pretty much second nature to me know so not sure I could do a good job of breaking them out, but it's good stuff like:

- thou shalt not use asynchronous inputs
- thou shalt not gate clocks
- thou shalt not use latches
- thou shalt provide default states for FSMs

etc.

Oh, and those that sometimes struggle with synchronizing your inputs.....yeah, that's a more complex subject than most novice's realize. I have read (and could probably even write one at this point) 20 page white papers on the subject. It's not a trivial thing so don't be frustrated thinking it should be so obvious.

[Mechatrommer]

ok maybe i forgot to ask earlier. whats the difference cpld and fpga? iirc i read about fpga we have to load the firmware from flash each time startup, cpld got its own memory. i maybe mistaken. but what about difference in architecture, or when to use cpld and when more appropriate to use fpga?