Author Topic: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...  (Read 7424 times)

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Offline Yansi

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Hello!
I am finishing my small CPLD development board and finaly got some testing to do. I have made a simple 4bit counter in VHDL, clocked by a GCLK2 pin. But it doesn't work at all. With clocks on GCLK1, the counter runs fine.

The board provides two clocks to the CPLD:  GCLK1 is 2048Hz, GCLK2 is 2Hz. Both signals are present directly on the chip pins (verified with scope, many times).

Why doesn't my design work with pin 40 (GCLK2) as a clock input?

I see that the GCLK2 pin is also shared with anothe dedicated function (OE2). Have I missed some settings in Quartus?

Sorry for such stupid questions, I am only a programmable logic greenhorn.

Thank you,
Yan
« Last Edit: January 02, 2016, 12:42:39 pm by Yansi »
 

Offline Yansi

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Re: Altera EPM3064 CPLD, GCLK2 pin doesn't work? why?
« Reply #1 on: January 01, 2016, 05:11:51 pm »
A small update:

As the only pins I have free on the CPLD are 38 (OE1) and 39 (GCLRN), I have tried connecting those to the 2Hz clock right there.

Guess what! It works, no issues clocking from these pins.  Why the hell is pin 40 (OE2/GLCK2) not working?

Yan


EDIT:
The hell why also pin 42 does not work?

Forget that, the device gets replaced.
« Last Edit: January 01, 2016, 06:08:14 pm by Yansi »
 

Offline Yansi

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Re: Altera EPM3064 CPLD, GCLK2 pin doesn't work? why?
« Reply #2 on: January 01, 2016, 06:52:27 pm »
You're right of course. But I'm trying to absorb some basic knowledge of programmable logic. So it is a good practice to learn what should be connected where. And it wasn't so much of a trouble at the PCB design stage to connect the clocks to the right pins, so I left the clocks where they should be, in a potentialy fast clocked application.

Note: So low clock frequency was chosen due to the fact the CPLD is very small (64 macrocells), so there is not much space for long clock dividers if someone wants to make a counter with human-recognizable output on my CPLD kit.



I have replaced the chip and the issue has gone. So a success. You can scrap this thread, useless.

When I found another pin (or maybe pins?) behaving strange, I knew the device must be faulty. (At the stage I knew only the pin 40 (GCLK2/OE2) hasn't been working, I thought there might be some issue with incorrect "settings" somewhere in the project, hence my stupid question)

Y.
« Last Edit: January 01, 2016, 06:55:04 pm by Yansi »
 

Offline Yansi

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After playing with the PLD a while, I have found just other issue with the new chip. When using macrocells near pins 8, 13 or 15 it even fails to program it. Otherwise the device works fine.

Whatta?!

Those devices are a load of horseshit. (or I got a load of horseshit)


Let's try soldering another one and see what happens.
 

Online nctnico

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Sounds more like you forgot some of the power/ground pins or a pin which needs a pull-up / pull-down doesn't have one.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline Yansi

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If that would be the case, I would really be happy. Unfortunately, I don't think so. The reason is that each device I tried has completely different issue.

This is the list of observed issues:
1st one: pin 40 (GCLK2) not working.
Device 2: Programing of the device fails if using pins 8, 13 or 15.
Device 3: Another whole bunch of pins don't work. (2, 3, 5, 6 and maybe more).

Here are the connections around the chip. I have double or maybe tripple checked, you can do too if you want. All VDD/GND pins connected and decoupled, correct pin numbers, JTAG working fine (pulldown on CLK, pullup on TMS), ...

I can't help myself, those devices must be garbbage. If I forgot to mention, they were bought from Aliexpress at a reasonable price. I frequently buy stuff from there, has bought maybe hundreds of pieces of semiconductors from there but this has never happened to me, to have a lot with 100% components failed. Only once I got one chip in a lot that had a damaged pin, but that might have been my fault.

I bought a lot of 10pcs at 11.8USD.  Same devices (EPM3064ATC44-10N) are on mouser.com at 2.92USD a piece, no discounts for larger quantity.
I also bought a lot of MAX II CPLDs (EPM240T100) at about 2$/pc, there were no issues with them whatsoever. (Mouser price for these is from about $8 up).
« Last Edit: January 02, 2016, 01:59:02 pm by Yansi »
 

Offline AndyC_772

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I've never, ever had a problem with the programming or operation of a MAX3000 device. They're certainly not defective "by design".

Try ordering a few devices from a reputable distributor.

If these work, then you (and anyone else considering buying from the same source) have learned a useful lesson about the dangers of buying from non-franchised sources that have no traceability back to the original manufacturer.

If they don't work either, then you have a board design and/or manufacturing problem. Maybe you have a defective PLCC socket? Poor ESD handling procedures?

Offline Yansi

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Yea, 5pcs are already on order list from Mouser.

There is no PLCC socket (hate these packages), these are TQFP44.

I think this is not an ESD problem, even that my home lab is quite poor at ESD precautions. Still I managed not to destroy or damage anything over the years. So I think there should be no difference with these devices. That was just a garbage lot.  |O

And also when talking about "learning a lesson" with Aliexpress, you might consider reading my other rant thread just right here:
https://www.eevblog.com/forum/chat/aliexpress-new-'advanced-search'-sucks-a-lot!/

Combined all together (ultra long delivery delays, crippled unusable search tool, some garbagge sellers too :-) ) this service has now really exceeded what I like to bear. Bastards...
« Last Edit: January 02, 2016, 02:30:43 pm by Yansi »
 

Offline Kalvin

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You may find this interesting, although it doesn't directly suggest that you are experiencing the same problems:

http://www.alteraforum.com/forum/showthread.php?t=20441

- TCK with pull-down, TMS and TDI with pull-up, TDO, VCC and GND.
- Particularly missing or too high resistance TCK pull-down is often causing problems.

You may have also written the VHDL / Verilog so that it synthesises something that is causing problems due to the actual on-chip delays.
« Last Edit: January 02, 2016, 04:09:28 pm by Kalvin »
 

Offline Yansi

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There was suggested a 10k for those pull up/downs, so I have respected that. TDI is floating. If I remember the manual right, there was no suggestion to pull the TDI anywhere. And from the common sense of the thing, floating the TDI should not cause any issues, while the TCK and TMS are pulled to a safe levels.

I have used the same JTAG scheme before with EPM240 CPLD, there were no issues involved.

I have tested all of the devices with various logic, including simple elements like connecting a pin directly to another in that HDL design. Even in that  case the mentioned pins weren't working.  When I experienced problems with programing one of the devices, I tested anything what came to mind, but ruled out error in the software quickly. The HW was clearly faulty.

Maybe until the end of the next week, I will probably have some pieces of the CPLD available - from Farnell. (My friend is making an order from there. Slightly more expensive, but at least it could finaly work. I hope so.)

//EDIT: It was this app note from Altera: https://www.altera.com/content/dam/altera-www/global/en_US/pdfs/literature/an/an100.pdf
And sorry, I was wrong, TCK has a suggested 1k pulldown, but I have increased it to 10k. This is no abnormaly noisy application, 10k must work, mustn't it?
« Last Edit: January 02, 2016, 04:54:05 pm by Yansi »
 

Offline Kalvin

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #10 on: January 02, 2016, 04:59:09 pm »
And sorry, I was wrong, TCK has a suggested 1k pulldown, but I have increased it to 10k. This is no abnormaly noisy application, 10k must work, mustn't it?

Test with 1k. But I would use the values which are recommended. :)
 

Offline Yansi

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #11 on: January 02, 2016, 05:35:49 pm »
There is no need to test that. Three of 4 devices programmed well, one fails programming and fails ONLY if some specific macrocells are used, otherwise programs well too.

The device has been already desoldered, discarded, PCB cleaned and ready for a new one from Farnell. So I can't test it anyway...

I am looking forward for the new parts...
« Last Edit: January 02, 2016, 05:38:28 pm by Yansi »
 

Offline marshallh

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #12 on: January 03, 2016, 05:37:35 am »
EPM3k series and EPM7k series were used for the original University Program boards. But they are rated only for max 100 program cycles... You begin to see the problem.

After several years there was a file cabinet full of at least 70-80 dead boards. They are fine for production. But for prototyping there is literally no reason to not use a modern FPGA-based pld.

Always assume any chips bought from ebay or any source besides a real supplier will be used pulls or factory rejects.
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11:37 <@ktemkin> He speaks protocols directly.
 

Offline Bruce Abbott

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #13 on: January 03, 2016, 06:04:27 am »
I am finishing my small CPLD development board
What is the purpose of your board? It appears to have a bunch of useless stuff on it (switches, push-buttons, 7 segment LEDs etc.). Can it do anything useful?

Quote from: marshallh
They are fine for production. But for prototyping there is literally no reason to not use a modern FPGA-based pld.
Xilinx XC9500 series CPLDs don't have that problem. >10,000 program/erase cycles should be enough!
 
 

Offline Yansi

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #14 on: January 03, 2016, 11:14:17 am »
who you are to judge usefulness of other's boards?  :--
 

Offline diyaudio

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #15 on: January 03, 2016, 12:41:45 pm »
Hello!
I am finishing my small CPLD development board and finaly got some testing to do. I have made a simple 4bit counter in VHDL, clocked by a GCLK2 pin. But it doesn't work at all. With clocks on GCLK1, the counter runs fine.

The board provides two clocks to the CPLD:  GCLK1 is 2048Hz, GCLK2 is 2Hz. Both signals are present directly on the chip pins (verified with scope, many times).

Why doesn't my design work with pin 40 (GCLK2) as a clock input?

I see that the GCLK2 pin is also shared with anothe dedicated function (OE2). Have I missed some settings in Quartus?

Sorry for such stupid questions, I am only a programmable logic greenhorn.

Thank you,
Yan

I dont know much about CPLD`s or FPGA`s , however this response is pretty generic.
 
I recently had an impressive first time success with a custom SHARC DSP board recently, I also never owned a dev board to perform reference checks against my design (only the dev board schematics) so the rate of failure was very high.

This is how I overcame uncertainty, and installed confidence when the PCB Gerber`s was sent off for manufacturing.

1) Obtain the manufacturing development board. study the area of interest well. psu, processor, pcb layout, test points the whole
dam thing.

2) Read and study the datasheet(s) of all the parts specifically the main processor or all the chips of interest to you that you going to incorporate in your design, try and isolate Signal, Power and Ground  with respect to the development board. (get into the head of what the designer was trying to achieve ) I printed out the PIN layout on a A4 paper and place markers of different colours on the PIN mapping to become familiar with all the power/ground rails and signal layers.   

3) Use a PCB layout tool like Altium Designer and set up rules for Power, Signal, Ground... (This helped me drastically identifying incorrect pin assignments or floating power/ground PINS) take into consideration it was a 144-PIN at 0.4mm pin pitch. Note these rules can only make sense if 1) and 2) was performed diligently reading the datasheet.

Iterate over until all common sense house keeping is dealt with. send off thy Gerbers and say a EE prayer before and after soldering.

 
   


« Last Edit: January 03, 2016, 12:47:33 pm by diyaudio »
 

Offline Yansi

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Re: Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...
« Reply #16 on: January 03, 2016, 06:15:07 pm »
The above mentioned works only if parts are genuine and not a bamboo & rice horseshit lot.

I am pretty confident with my design. I am quite sure the testing procedures I have made ruled out any HW design issues, so did they rule out SW issues. I might be wrong, thats possible, but we will see when the new parts arrive.

I will not further comment this, until I will make a test with chips from Farnell.  Any disccusion until that lacks sense I think, as we would only argue what might or might not happened.
 


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