Electronics > FPGA

Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...

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Kalvin:

--- Quote from: Yansi on January 02, 2016, 04:50:23 pm ---And sorry, I was wrong, TCK has a suggested 1k pulldown, but I have increased it to 10k. This is no abnormaly noisy application, 10k must work, mustn't it?

--- End quote ---

Test with 1k. But I would use the values which are recommended. :)

Yansi:
There is no need to test that. Three of 4 devices programmed well, one fails programming and fails ONLY if some specific macrocells are used, otherwise programs well too.

The device has been already desoldered, discarded, PCB cleaned and ready for a new one from Farnell. So I can't test it anyway...

I am looking forward for the new parts...

marshallh:
EPM3k series and EPM7k series were used for the original University Program boards. But they are rated only for max 100 program cycles... You begin to see the problem.

After several years there was a file cabinet full of at least 70-80 dead boards. They are fine for production. But for prototyping there is literally no reason to not use a modern FPGA-based pld.

Always assume any chips bought from ebay or any source besides a real supplier will be used pulls or factory rejects.

Bruce Abbott:

--- Quote from: Yansi on January 01, 2016, 02:51:15 pm ---I am finishing my small CPLD development board
--- End quote ---
What is the purpose of your board? It appears to have a bunch of useless stuff on it (switches, push-buttons, 7 segment LEDs etc.). Can it do anything useful?


--- Quote from: marshallh ---They are fine for production. But for prototyping there is literally no reason to not use a modern FPGA-based pld.
--- End quote ---
Xilinx XC9500 series CPLDs don't have that problem. >10,000 program/erase cycles should be enough!
 

Yansi:
who you are to judge usefulness of other's boards?  :--

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