Electronics > FPGA

Altera EPM3064 CPLDs suck - but why? Maybe I got a lot of garbagge ones...

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diyaudio:

--- Quote from: Yansi on January 01, 2016, 02:51:15 pm ---Hello!
I am finishing my small CPLD development board and finaly got some testing to do. I have made a simple 4bit counter in VHDL, clocked by a GCLK2 pin. But it doesn't work at all. With clocks on GCLK1, the counter runs fine.

The board provides two clocks to the CPLD:  GCLK1 is 2048Hz, GCLK2 is 2Hz. Both signals are present directly on the chip pins (verified with scope, many times).

Why doesn't my design work with pin 40 (GCLK2) as a clock input?

I see that the GCLK2 pin is also shared with anothe dedicated function (OE2). Have I missed some settings in Quartus?

Sorry for such stupid questions, I am only a programmable logic greenhorn.

Thank you,
Yan

--- End quote ---

I dont know much about CPLD`s or FPGA`s , however this response is pretty generic.
 
I recently had an impressive first time success with a custom SHARC DSP board recently, I also never owned a dev board to perform reference checks against my design (only the dev board schematics) so the rate of failure was very high.

This is how I overcame uncertainty, and installed confidence when the PCB Gerber`s was sent off for manufacturing.

1) Obtain the manufacturing development board. study the area of interest well. psu, processor, pcb layout, test points the whole
dam thing.

2) Read and study the datasheet(s) of all the parts specifically the main processor or all the chips of interest to you that you going to incorporate in your design, try and isolate Signal, Power and Ground  with respect to the development board. (get into the head of what the designer was trying to achieve ) I printed out the PIN layout on a A4 paper and place markers of different colours on the PIN mapping to become familiar with all the power/ground rails and signal layers.   

3) Use a PCB layout tool like Altium Designer and set up rules for Power, Signal, Ground... (This helped me drastically identifying incorrect pin assignments or floating power/ground PINS) take into consideration it was a 144-PIN at 0.4mm pin pitch. Note these rules can only make sense if 1) and 2) was performed diligently reading the datasheet.

Iterate over until all common sense house keeping is dealt with. send off thy Gerbers and say a EE prayer before and after soldering.

 
   


Yansi:
The above mentioned works only if parts are genuine and not a bamboo & rice horseshit lot.

I am pretty confident with my design. I am quite sure the testing procedures I have made ruled out any HW design issues, so did they rule out SW issues. I might be wrong, thats possible, but we will see when the new parts arrive.

I will not further comment this, until I will make a test with chips from Farnell.  Any disccusion until that lacks sense I think, as we would only argue what might or might not happened.

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