Altera on board USB blaster

[Wiljan]

I have a Cyclone V GT FPGA Development Board
https://www.intel.com/content/www/us/en/programmable/products/boards_and_kits/dev-kits/altera/kit-cyclone-v-gt.html

The board had a broken MAX II and MAX V due to some short circuit some years ago and the MAX II and MAX V did short the voltage reg.

The 2 chips was removed and all voltage went back to normal and the Cyclone V does work fine but need to be programmed with a external USB blaster, again that works fine...

BUT it's very slow (JTAG) compared to the on-board Blaster (which does load in parallel).

Link for schematic (page 19 shows the On-Board USB Blaster II)
https://www.analog.com/media/en/technical-documentation/eval-board-schematic/c5gt_pcie_b.pdf

So I have got a new MAX II chip which I have soldered to the dev board and when using the USB cable to the board windows does recognize the uP which are on the dev board as USB interface the MAX II.

So my question is... how is the MAX II programmed on the dev board?

Is that done automatic via the USB driver and via the uP or does the it need to be programmed via JTAG somehow?

In the dev board files there are images for the MAX V and the Cyclone but nothing for the MAX II or the uP CY7C68013A, it might be proprietary

Hope it makes sense

[aandrew]

It looks like the MAX II is programmed via the FX2LP (take a look at the lower-right corner of U49A and note how it runs to the FX2LP's PORTD pins.

Altera/Intel have always kept the bitstream of the CPLD in their blasters proprietary, so it does not surprise me that you can't find it. I'm a little surprised that they don't have a way to update the bitstream "in the field"; you may need to contact your rep to see if they can share a tool to do so.

On my own MAX10 designs I have included an FTDI FT2232 and use a specific config image for the FTDI. Along with a binary PC library that Arrow had provided, this allows me to have an on board JTAG tool which Quartus recognizes. This is great because I can use SignalTap without having to use an external debugger.

[Wiljan]

@ aandrew  yes I did notice the JTAG connection between the MAX II and the FX2.

So either a bitstream and a soft for the PC are required rto flash the MAX II once

Or the USB driver  just download the bitstream each time it's loaded

Or the FX2 (CY7C68013A) does have it in the flash and push it to the MAX II

I have  DECA dev board as well and did see in the schematic that it's done with the same FX2 but a MAX V instead.
I could try to look on the JTAG there and see is they push something on each power-cycle

Sure it could be worth to ask Intel for a solution