Altera orcad library

[ayansengupta17]

I am absolutely new to FPGA devices, so please excuse me for novice questions.

I am designing a FPGA board using EP1C12Q240C8 of cyclone 1 device.

I am using orcad capture for designing the schematic. I found this particular library for this model from Altera site.
http://www.altera.com/download/board-layout-test/pcb/pcb-cadence.html

Now the problem is, in this model, there are 60 pins on each side of the FPGA, but in the orcad library given by altera, the pins are arranged haphazardly, not like the original device. I have attached a screenshot of the orcad library image.

 

please help me.

[millerb]

Just bite the bullet and roll one yourself. You can easily spend 10x more time and effort trying to find a solution on the net for this kind of stuff.

[AndyC_772]

It looks like the pins on Altera's own symbol are arranged to as to group the I/O banks together. When I do FPGA symbols I even go a stage further and create a separate gate (symbol) for each bank, plus one for power. You'll find grouping them this way much clearer than just arranging the pins on the symbol by physical position on the chip.

If you still want a symbol that's different to the Altera provided one, you need to set aside some time and get on with it. There is no alternative, nobody is going to do it for you. Here's the pinout details for the 1C12, though I'd urge to you use a device which isn't already obsolete if at all possible:

http://www.altera.com/literature/dp/cyclone/ep1c12.txt

[nctnico]

There is always a debate whether a symbol should show functional groups or show the chip as it is on the PCB. Personally I prefer the symbol to look like the chip because it makes measuring in a circuit much easier. Ofcourse its not possible for every chip (BGA packages) but then again you can't probe a BGA package anyway.

[ayansengupta17]

Finally i want to make a pcb from the schematic, so its better if i could get a library where the pins are actually similar to the real  pin configuration!

[AlfBaz]

There is always a debate whether a symbol should show functional groups or show the chip as it is on the PCB. Personally I prefer the symbol to look like the chip because it makes measuring in a circuit much easier. Ofcourse its not possible for every chip (BGA packages) but then again you can't probe a BGA package anyway.

Love to hear a debate on it. I strive for functional grouping, and do exactly as Andy for FPGA's but mcu's with multiple functions per pin, creating a symbol that suites every application is hard to do, especially if you want to avoid joining wires with net names. Unlocking symbol primitives and moving pins is another option, but you're just asking for trouble if you like to sync to libraries to pull in any extra data such as supplier, cost etc..

[AndyC_772]

I suspect such a debate could go downhill very quickly indeed!

I have 'house rules' which I always follow when naming pins and drawing symbols, but I'm hesitant to post them on a public forum because someone is bound to take offence and question my professionalism, ethics, parentage and so on. In my experience it's an emotive subject.

Grouping pins by function rather than by physical position on the chip does seem sensible to me, though - but if it suits another engineer's purposes to draw the symbol differently then I wouldn't argue. That is, of course, unless I'm also going to have to work with the same schematic, in which case my response would depend on who is the senior engineer and/or who is the customer at the time...

[nctnico]

A lot of the time can go into debugging a circuit so make that as easy as possible. When the symbol is like the actual device then it is easier to debug because you don't need to lookup the pin locations of the chip.

Another advantage of using the actual devices is that it is easier to optimise the PCB layout at the design stage. If the schematic is cluttered then the PCB will most likely to be hard to route. When I design something I like to keep the bottom layer as a solid ground plane so basically my designs are optimised to be single layer designs. Imagine you need to connect a memory chip to an FPGA. When the symbols are like the actual devices then you can already create the most optimal connections without needing to go back and forth between the PCB and the schematic to do pin swaps.

[Rufus]

Grouping pins by function rather than by physical position on the chip does seem sensible to me, though

The problem is obviously the stupid chip manufacturers. I mean what clown would scatter VDD and GND pins all around the chip instead of keeping them next to each other where they are easy to connect? Don't know why they need more than one of each anyway.

[nctnico]

Power and ground are distributed using the metalic layer on the chip. Although these are all connected the resistance and self inductance are not zero so multiple pins are needed to keep the supply voltage within tolerances.

[AlfBaz]

I guess it would also depend on the software package you are using, some would lend themselves to greater flexibility.

As a hobbyist with no industry experience I find there are way to many ways of doing things and consequently chop and change methods from project to project, high time I documented my workflow and some self imposed standards

I have 'house rules' which I always follow when naming pins and drawing symbols, but I'm hesitant to post them on a public forum because someone is bound to take offence and question my professionalism, ethics, parentage and so on. In my experience it's an emotive subject.

It's a shame, it would be nice to see what others are doing or at least examples of procedure in place at professional houses.

A lot of the time can go into debugging a circuit so make that as easy as possible. When the symbol is like the actual device then it is easier to debug because you don't need to lookup the pin locations of the chip.

Cross probing can help if you have access to the schematic/pcb file and the cad software it was designed in, but I agree, it's not optimal. This method would certainly make choosing a symbol layout a lot easier

[AlfBaz]

The problem is obviously the stupid chip manufacturers. I mean what clown would scatter VDD and GND pins all around the chip instead of keeping them next to each other where they are easy to connect? Don't know why they need more than one of each anyway.

I've read other posts by you Rufus, you are not a chump, so you must be taking the piss here 

[lorth]

The problem is obviously the stupid chip manufacturers. I mean what clown would scatter VDD and GND pins all around the chip instead of keeping them next to each other where they are easy to connect? Don't know why they need more than one of each anyway.

I've read other posts by you Rufus, you are not a chump, so you must be taking the piss here 

I hope... xD