Need help with Altera NIOS II processors.

[palpurul]

Hello,
I've been hopelessly trying to implement NIOS II processor in my de10-lite FPGA board and I haven't succeeded thus far. I tried various tutorials and tried different versions of quartus, but somehow I didn't get it right. I get the following error:

Error (11176): Alt_sld_fab.: version not allowed for EModuleProperty (full version of this attached)

I asked this in Altera's forum and I didn't get any help. There are a few similar threads in Altera's forum they all seem dead with no solution to this problem.
Has anyone had any experience with NIOS 2 processors? Anyone encountered this problem before?

[Daixiwen]

Which version of Quartus are you using? Can you share the whole project? (you can create an archive from the project menu)

[palpurul]

I think .qar file is what you are asking for. I am using quartus 16.0, but I used 18.0 as well. No change.
I attached the .qar file to my reply.

[Daixiwen]

Well this is strange. I imported your archive in my version of Quartus (16.1) and didn't run into your problem. I had another error instead:

Error (14703): Invalid internal configuration mode for design with memory initialization

I'm not familliar with the Max10 so I don't know what exactly is Quartus' deal with memory initialization but just for the test I disabled the memory initialization in the on_chip_memory_0 component in Qsys, regenerated and recompiled, and this time it went all the way through without any error.

Could it be a problem with your Quartus installation? Can you try and reinstall it?

Do you have a license for the Nios II processor? If not, when selecting the Nios II/f it will generate a time limited compiled image that needs to stay connected to the USB blaster to work, and maybe this part is triggering a bug in Quartus Try selecting the Nios II/e core instead and check if this changes anything. The Nios II/e core doesn't require any extra license. Don't forget to regenerate in QSys before you recompile your project in Quartus.

[palpurul]

Well this is strange. I imported your archive in my version of Quartus (16.1) and didn't run into your problem. I had another error instead:

Error (14703): Invalid internal configuration mode for design with memory initialization

I'm not familliar with the Max10 so I don't know what exactly is Quartus' deal with memory initialization but just for the test I disabled the memory initialization in the on_chip_memory_0 component in Qsys, regenerated and recompiled, and this time it went all the way through without any error.

Could it be a problem with your Quartus installation? Can you try and reinstall it?

Do you have a license for the Nios II processor? If not, when selecting the Nios II/f it will generate a time limited compiled image that needs to stay connected to the USB blaster to work, and maybe this part is triggering a bug in Quartus Try selecting the Nios II/e core instead and check if this changes anything. The Nios II/e core doesn't require any extra license. Don't forget to regenerate in QSys before you recompile your project in Quartus.

I am using the free version. I tried NIOS 2/e and I get the same error. I didn't know NIOS 2/f requires paid licence in some cases. I better stay away from it. I follow 2 different tutorial on how to implement NIOS 2 and I followed it step by step nothing worked. strangely, they use the same version of quartus and they don't have any license. Just wierd.

I tried 2 different versions of quartus nothing really changes, tried reinstall a few times nothing changed. Should I try 15.0 also. Is there any "least painful" version of quartus?

[Daixiwen]

You can use the Nios II/f without license, but it generates additional logic to enable the "opencore plus evaluation mode", where your design needs to be connected permanently to a USB blaster, or the CPU will stop. As your error message seemed to be related to a JTAG module I thought this could be the issue.
As for the version, I find all versions of Quartus equally painful . Do you have sample projects with your kit that you could try and compile?

[palpurul]

You can use the Nios II/f without license, but it generates additional logic to enable the "opencore plus evaluation mode", where your design needs to be connected permanently to a USB blaster, or the CPU will stop. As your error message seemed to be related to a JTAG module I thought this could be the issue.
As for the version, I find all versions of Quartus equally painful . Do you have sample projects with your kit that you could try and compile?

"equally painful" that's a nice way yo put it. I hate the time when I start to use a new development tool to start programming something. They are almost always very difficult to start.

I tried different examples from Altera desing stores for my development board. They have bunch of different examples involving NIOS II, but none of them compiled. Some of them gave me differen errors some of them gave me the same errors.

Not sure what's going on and Altera won't help me  .

What should I try next? different vendor?

[palpurul]

I'll try it in a different computer when I got home. Let's hope that it compiles this time.

[Scrts]

Are you using SignalTap logic analyzer as well?

[palpurul]

Are you using SignalTap logic analyzer as well?

I think I'm not. Not really sure.
How do I check this?

[palpurul]

I'll try it in a different computer when I got home. Let's hope that it compiles this time.

Not suprisingly, no change.

[Daixiwen]

Are you using SignalTap logic analyzer as well?

I think I'm not. Not really sure.
How do I check this?

If you didn't create a signaltap project and include it (it's a *.stp file) in your FPGA project then the answer is no. You can always check in the assignment > settings > SignalTap II Logic Analyzer window.
It wasn't used in the project archive you sent.

I was actually wondering that too, especially since your error message seems to come from somewhere around a virtual JTAG module, but I think it is actually the OpenCore evaluation module for the Nios II/f. That's why I hoped that switching to the license free Nios II/e would help.

[palpurul]

Are you using SignalTap logic analyzer as well?

I think I'm not. Not really sure.
How do I check this?

If you didn't create a signaltap project and include it (it's a *.stp file) in your FPGA project then the answer is no. You can always check in the assignment > settings > SignalTap II Logic Analyzer window.
It wasn't used in the project archive you sent.

I was actually wondering that too, especially since your error message seems to come from somewhere around a virtual JTAG module, but I think it is actually the OpenCore evaluation module for the Nios II/f. That's why I hoped that switching to the license free Nios II/e would help.

Nothing really worked so far. I am waiting for Altera support to help me. I update when the problem is solved.
Thanks for your help!