Alternatives to always@(posedge clk, negedge clk)

[gnuarm]

(Attachment Link) Ok, drawn with mouse so SET mousestate == jerky

and my first attachment so anything could happen. (Attachment Link)

@Chris_Mr

Someone told me this circuit that you suggested would not be able to generate 90 degree phase shift.
However, I am not convinced yet.

I am planning to get it works with the D flip-flops hardware primitives in sky130 PDK since pure verilog coding would not be able to model your circuit.



By the way, when I research further, it seems that digital PLL might not be needed at all in this context. Please correct me if wrong

https://patents.google.com/patent/US9158873
https://patents.google.com/patent/KR20050101864A/en
https://patents.google.com/patent/US7443741B2/en
https://patents.google.com/patent/US9001595

This circuit doubles the clock rate, then produces a 90° phase shift by dividing by four.  So in effect it halves the input clock rate to achieve the output clock rate using what is 180° phase shift relative to the incoming clock.

You can use the same logic without doubling the input clock rate and get an output clock rate that is a quarter of the input clock rate with 90° phase shifts. 

You can also get the same result of 90° phase shifts at half the clock rate without doubling the input clock by having one of the FFs operate on the falling edge of the clock. 

You can not get 90° phase shifts at the input clock rate by combining the clock rate doubling with the negative edge clocking because the frequency doubled clock does not have a 50/50 duty cycle or anything close to it.  In fact, that circuit is not guaranteed to work in any logic family.  It most likely is failing clock timing specifications and possibly voltage specifications. 

Oh yeah, you can simulate this from HDL inferred logic.  First simulate in a language simulator which will produce infinitely narrow clock pulses.  You can also simulate after synthesis using the primitives generated rather then instantiating primitives.

[langwadt]

why so hung up on 90 degrees? nothing happens at 90 degree, everything happens at 0 or 180 deg after some delay that varies and will have to be accounted for in each implementation

[Daixiwen]

The dedicated DDR memory controller IPs in FPGAs usually use a PLL with the possibility to finely adjust the phase shift between an "intern" clock that is used in the FPGA and the "extern" clock on the PCB. Then the calibration algorithm will adjust that PLL shift to have an optimal timing. The PLL is of course a vendor dependent primitive so you won't be able to describe this in a generic way in HDL. You will need to choose your target first and then see what primitives or controllers you can use.
Some FPGAs have ready made hardcore DDR3 controllers, and if you can use those it will save you a lot of time and pain.

[NorthGuy]

why so hung up on 90 degrees? nothing happens at 90 degree, everything happens at 0 or 180 deg after some delay that varies and will have to be accounted for in each implementation

DQ and DQS are sent by DDR3 chip in phase. DQS is not a clock, really, but rather a strobe which accompanies DQ. DQ changes at 0 and 180 degrees, so the sampling window is somewhere between 0 and 180 (with the middle at 90) and another one between 180 and 360 (with the middle at 270). If you want to use DQS to sample DQ (that is DQ goes to the D input of flip-flop and DQS goes to the CLK input of the flip-flop), you need to position DQS edges in the middle of the windows (that is at 90 and 270). Hence, it's necessary to shift DQS by 90 degrees.

[langwadt]

why so hung up on 90 degrees? nothing happens at 90 degree, everything happens at 0 or 180 deg after some delay that varies and will have to be accounted for in each implementation

DQ and DQS are sent by DDR3 chip in phase. DQS is not a clock, really, but rather a strobe which accompanies DQ. DQ changes at 0 and 180 degrees, so the sampling window is somewhere between 0 and 180 (with the middle at 90) and another one between 180 and 360 (with the middle at 270). If you want to use DQS to sample DQ (that is DQ goes to the D input of flip-flop and DQS goes to the CLK input of the flip-flop), you need to position DQS edges in the middle of the windows (that is at 90 and 270). Hence, it's necessary to shift DQS by 90 degrees.

still doesn't make 90 a significant number. What matters is sampling at the right spot when taking into account the output, input and wiring delays on DQ and DQS and what  the required setup and hold is on the flipflop

[NorthGuy]

still doesn't make 90 a significant number. What matters is sampling at the right spot when taking into account the output, input and wiring delays on DQ and DQS and what  the required setup and hold is on the flipflop

Of course, it doesn't have to be exactly 90 degrees. 90 is nominal.

DQS and DQ take different paths to the flop and thus encounter different delays with different uncertainties. These uncertainties may be far greater in magnitude than the phase shift you're trying to achieve. Therefore, by the time they arrive to the receiving flip flop, their phase relationship is not really known. The controller would typically use calibrated delays to align the signals to the middle of the window empirically.

[langwadt]

still doesn't make 90 a significant number. What matters is sampling at the right spot when taking into account the output, input and wiring delays on DQ and DQS and what  the required setup and hold is on the flipflop

Of course, it doesn't have to be exactly 90 degrees. 90 is nominal.

DQS and DQ take different paths to the flop and thus encounter different delays with different uncertainties. These uncertainties may be far greater in magnitude than the phase shift you're trying to achieve. Therefore, by the time they arrive to the receiving flip flop, their phase relationship is not really known. The controller would typically use calibrated delays to align the signals to the middle of the window empirically.

even in the case where the delays are the same 90 would only be nominal if setup and hold are the same

[NorthGuy]

even in the case where the delays are the same 90 would only be nominal if setup and hold are the same

"Nominal, adjective - (of a quantity or dimension, especially of manufactured articles) stated or expressed but not necessarily corresponding exactly to the real value."

[promach]

1. Do I really need tdqs and odt ?

2. Another question is do I need twr for write_AP ?

    by the way, I had done an initial code for the DDR3 memory controller in verilog :

    https://gist.github.com/promach/2c477b1dbc39f04a1271fb229e6d678c

[promach]

For Data strobe enable circuitry , in Figures 4 and 5 , how exactly does the DQS_Clean being phase-shifted 90 degrees with reference to DQS_P and DQS_N ? Why do we need the COUNTER module in which the circuit is described in Figure 5 ? What value should I assign for Vref ?