AMD/Xilinx announced their own RISC-V soft-core

[asmi]

https://www.xilinx.com/products/design-tools/microblaze-v.html

Configurable ISA support for RV32IMAFC Base Integer Instruction Set with optional:
- Multiplication and division ("M" extension)
- Atomic instructions ("A" extension)
- Floating-point ("F" extension)
- Code compression ("C" extension)
- Bit manipulation ("Zba", "Zbb", "Zbc", "Zbs" extensions)
Utilizes code compression to significantly reduce code size and save design memory
Offers three selectable configurations: microcontroller, real-time processor, and application processor*
Provides build options to optimize area and/or performance
Incorporates safety measures like dual-core lockstep and triple modular redundancy (TMR) for safety-critical systems

Apparently MCU configuration is already available to EA program participants (of which I am not), other are expected later. So not much is known about it at this point. But I totally expected this given the market trends.

[brucehoult]

MicroSemi have been offering both RISC-V soft cores since 2017 and hard cores (PolarFire SoC, in e.g. the new BeagleBoard Fire, Icicle) since late 2020.

Lattice announced their first official RISC-V soft core in I think June 2020 (collab with SiFive announced December 2019), and improved versions e.g. an 800 LUT core in mid 2021.

Intel/Altera introduced Nios V in October 2021

Xilinx is a little late to the party, but yeah they all seem to see very little value in having their own funky ISA, along with associated software ecosystem costs.

[SiliconWizard]

Yes the reason we all turn to RISC-V, beyond the fact it's a reasonably well designed ISA, is to leverage the ecosystem, which is a huge time and cost saver.

[brucehoult]

Yes the reason we all turn to RISC-V, beyond the fact it's a reasonably well designed ISA, is to leverage the ecosystem, which is a huge time and cost saver.

Reasonably well designed ... Good Enough. But even I have a list of things I would have done differently .. for example slt and sltu should return 0 or -1 not 0 or 1, 32 bit and 64 bit should be more compatible, the C extension should devote a lot less opcode space to FP (over-optimisation for SPECFP). But RV32I/RV32E do a remarkably good job for having only 37 instructions that a compiler might generate (ARMv6-M in CM0 has about 90, with little or no extra benefit), and the C extension is low implementation cost too.

[SpacedCowboy]

MicroSemi have been offering both RISC-V soft cores since 2017 and hard cores (PolarFire SoC, in e.g. the new BeagleBoard Fire, Icicle) since late 2020.

Lattice announced their first official RISC-V soft core in I think June 2020 (collab with SiFive announced December 2019), and improved versions e.g. an 800 LUT core in mid 2021.

Intel/Altera introduced Nios V in October 2021

Xilinx is a little late to the party, but yeah they all seem to see very little value in having their own funky ISA, along with associated software ecosystem costs.

Even relative minnows like Efinix have had soft-core RISC-V for ages (3 SOC variants IIRC) and have been promising hard cores in their larger (as yet unreleased) Titanium range. I think they’ve just got as far as Ti180, and the next one is the Ti240 with hardened processors.

[SiliconWizard]

Even relative minnows like Efinix have had soft-core RISC-V for ages

Yes, but so what? It's actually not really "even" that applies here. The small ones precisely go for RISC-V because this is the path of least cost and they probably would never have invested in designing their own cores otherwise.
It's understandable OTOH that the big ones that already had their own working proprietary soft cores for a long time have taken longer to provide RISC-V cores. It's just basic common sense.

[brucehoult]

I recall first hearing about RISC-V and looking at the ISA and encoding and not being that impressed in maybe 2012 -- I don't know exactly. I looked again in early December 2016 when SiFive announced the HiFive1 and was much more impressed. The ISA had changed a lot, and especially the C extension had been added. I bought one of the first batch of HiFive1, with signatures of all 17 SiFive employees on the back of the board.

While on a business trip from Samsung R&D Moscow to the San Jose office in October 2017 I found time after we'd done everything we'd (my boss and I) come for, and I called SiFive and asked if I could visit. They said "sure!" (I was fairly active in their forums) I dragged my boss along as he had nothing better to do. I didn't count the people but it can't have been more than 20. I had a long chat with Palmer, and then another with Megan. They invited us to come to dinner with them and others in Berkeley (quite a drive from San Mateo, or back to San Jose after). Krste and Andrew were there, and I think Chris "BOOM!" Celio, and I remember Jack Koenig (Chisel guy) with his arm in a cast. I saw most of them again a week later at CARRV in Boston where Michael Clarke and I (well, Michael) presented our rv8 paper. Three months later, while I was on vacation in NZ, at the after-flying BBQ at my gliding club, Yunsup called and said "We really should do something about hiring you". [1] The H-1B paperwork said there were 31 employees.

When Krste first started talking about "Modest RISC-V Project Goal: Become the industry-standard ISA for all computing devices" [2] and "World domination" it seemed like crazy talk.

And yet, here we are. The momentum is incredible, and penetration in lower end markets is getting serious.

Not in phones or PCs or datacenter servers or supercomputers yet, but they all look as if they're going to happen, with Android Wear OS coming soon and full Android not far behind. Half a dozen serious companies are aiming at current (or at least recent) x86/Apple performance levels.

This raises a big question: can anything else in future repeat this and displace RISC-V?  Or is this a oncer, and RISC-V will evolve and be used for as long as IBM 360 has (60 years in April 2024) or longer?


[1] has anyone else ever accidentally taken their current boss to what was effectively their interview for a new job? Sitting in the same meeting room even, and sometimes participating in the conversation. Lol.

[2] at least as early as January 2015: https://www.slideshare.net/RISC-VFoundation1/riscv-software-state-of-the-union#4

[SiliconWizard]

This raises a big question: can anything else in future repeat this and displace RISC-V?  Or is this a oncer, and RISC-V will evolve and be used for as long as IBM 360 has (60 years in April 2024) or longer?

A corollary question is, with all the traction it is getting, is RISC-V not going to eventually be "captured" one way or another by one (or just a few) big fishes and, despite its inherent merits, just become what every other ISA has become?
Is it always going to remain open? What guarantee is there? I know the RISC-V foundation has gone to Switzerland already, and that wasn't just for the chocolate and the lakes.

[brucehoult]

Capture is certainly a theoretical possibility. But how would it happen?

Some company makes a proprietary extension that is SO COMPELLING that no one wants to be without it?

I can't see what else could do it.

The problem is ... what would that extension be? RISC-V already has standard extensions ratified or in progress for pretty much anything that any other ISA has.

I guess someone could come up with some new implementation technology that vastly improves speeds -- optical or quantum or whatever -- but that's equally likely (at least) to be applied to x86 or Arm not RISC-V.

[DiTBho]

Yesterday someone parked a very big and heavy parcel in front of my office door.

W__H__A__T__T__H__E__F__R__O__G__? 

I was taking the coffee with the new sweden girl hired as secretary for my floor, who, as first job task, simply had forgotten to inform me about the parcel on delivery. But, it's too nice and very young (24yo), so can be forgiven.

Anyway, it took me 45 minutes to unbox and get it started with 128 ARM cores and 96GByte of ram, not because the "CPU" is bigger than everything we have ever called "CPU" ... but - look there - she stopped, waved her hand, standing on tiptoe, probably to ask me what the hell those bumps were on the ceramic of a CPU that didn't look like an ordinary CPU, and I think in response to her gesture my face responded like the Machintosh when it crashes, because precisely at that point she put her heels back on the ground, but her eyes look a little disappointed that we both had absolutely no idea - it looks like a small aircraft carrier, with lots of protrusions on top  - she decided with a smile - that look just like many small planes parked and ready to take off! - in the whiteness of her very white teeth, reminded me of Shirley Manson wearing the "I heart nerds" t-shirt.

(+1 to be forgiven when she makes a mistake!)

Anyway, ... it took me 45 minutes to unbox and get it started ... not because it is difficult to install the "aircraft carrier" on a dedicated ultra-high-density socket, not because it is difficult to apply thermal paste and install the liquid cooling system head, not because it is difficult to install the liquid coolant and take it for a test drive to check that there are no leaks, but why... the machine I use every day is a 2005 Apple MDD, with two G4 CPUs, 2GB of RAM, which in my small way looks like a spaceship.

So you understand... I find it quite shocking to go from 2 CPUs to 128 CPUs, and I find it even more shocking to go from 2GB to 96GB.

It's the new Ampera computer, this time @3Ghz. Unfortunately it's not mine. It's a R&D machine I have to support with a fresh Gentoo/Arm stage4.

I set aside 7000 euros because I wanted to buy a POWER9 with 32 cores, it's a lot of money, but it's still not enough to *import* two CPUs and a server-profiled motherboard from the USA, as you have to also buy ram, PSU, HDDs, a case, a video card, ... , but then I changed my mind, and I'm waiting for the day that something similar to that Ampera-monster but with 128core RISC-V comes out.

The problem? Well, well, well, ... extensions to make those cores speak in a competitive way, without penalizing themselves in useless waits.

I am waiting for this

[brucehoult]

> I'm waiting for the day that something similar to that Ampera-monster but with 128core RISC-V comes out.

Milk-V Pioneer with the 64 core SG2042 is supposed to ship within the next month. I've been using one (or at least SOPHON's own dev board) vis ssh to China since March.

The cores are only Arm A72 class, but it runs pretty well. Even on single-threaded the 64 MB L3 cache makes it a lot faster than the Lichee Pi 4A with the same C910 cores. On highly threaded code it's competitive in total throughput with current 12 or 16 core x86, for about the same system cost too.

Others are coming out with at least dual-socket boards with the same SoC (so 128 cores), and I think also quad-socket (256 cores).

Of course the Ampere is using Neoverse N1 cores which are quite a bit faster.

[asmi]

The cores are only Arm A72 class, but it runs pretty well. Even on single-threaded the 64 MB L3 cache makes it a lot faster than the Lichee Pi 4A with the same C910 cores. On highly threaded code it's competitive in total throughput with current 12 or 16 core x86, for about the same system cost too.

Hmm, so currently the best RV core is about 4 times slower than x86? That means things are much worse than I expected. The whole point of RISC is supposed to be that it can be made very fast since instructions are very simple, so RV core has to have much better IPC than x86 in order to compete with it, since x86 instructions do more than RV one. And you can never compensate for slowness of a core with higher core count as great many tasks rely on a single thread, or a handful of threads, and do not scale across many cores.

[brucehoult]

Hmm, so currently the best RV core is about 4 times slower than x86?

The best one shipping in volume, mass production, right now. Arm A72 class. The core was announced in July 2019.

SoCs/boards in A76 class (similar to RK3588 in the Rock 5 and Orange Pi 5  and the BMC in the Pi 5) are expected to ship in the next six months (probably we'll hear more at the RISC-V Summit this week).

SOPHON has announced a chip with 16 SiFive P670 cores -- Arm A78 class -- which they say will ship before the end of 2024.

SiFive's latest core, P870, announced in October, in in Cortex X3 class. That's the top of Arm's current game.

Multiple credible well funded companies (Tenstorrent, Rivos, Ventana, even MIPS) have announced or will soon announce cores in recent x86/Apple M1/2 performance range e.g. 8 wide.

All those can be expected to be available in expensive dev board form in 2024 or 2025, and mass production 2026 or 2027.

Don't forget the ISA has only existed in frozen form since July 2019, just over four years.

[SiliconWizard]

You can't beat decades of experience designing CPU cores within just a few years. Come on. The ISA itself is relevant to an extent, but not *that* much.
And all that without infringing on myriads of patents.

[brucehoult]

You can't beat decades of experience designing CPU cores within just a few years. Come on. The ISA itself is relevant to an extent, but not *that* much.

Companies don't have experience designing CPU cores, engineers do, and engineers are mobile and don't suddenly forget everything when they change companies.

Look at just one RISC-V company, Tenstorrent. CTO Jim Keller is an industry legend. He was instrumental in Intel's Ice Lake and Lakefield CPUs and before that in AMD's first Zen cores, not to mention Athlon (K7) and then Opteron (K8/Sledgehammer) 20+ years ago. In between he was at Tesla and Apple (A4&A5). Tenstorrent also has Wei-han Lien, lead architect of Apple's M1.

What makes you think those guys have forgotten how to design high performance cores, just because they're working with RISC-V now?


Rivos and Ventana also have plenty of engineers with recent experience designing high performance cores at places such as Apple, AMD, Intel, and Arm. Not to mention MIPS who have never had problems making fast chips, just selling them. They're doing RISC-V now too and have announced an 8-wide decode core.

[asmi]

The best one shipping in volume, mass production, right now. Arm A72 class. The core was announced in July 2019.

SoCs/boards in A76 class (similar to RK3588 in the Rock 5 and Orange Pi 5  and the BMC in the Pi 5) are expected to ship in the next six months (probably we'll hear more at the RISC-V Summit this week).

SOPHON has announced a chip with 16 SiFive P670 cores -- Arm A78 class -- which they say will ship before the end of 2024.

SiFive's latest core, P870, announced in October, in in Cortex X3 class. That's the top of Arm's current game.

Multiple credible well funded companies (Tenstorrent, Rivos, Ventana, even MIPS) have announced or will soon announce cores in recent x86/Apple M1/2 performance range e.g. 8 wide.

All those can be expected to be available in expensive dev board form in 2024 or 2025, and mass production 2026 or 2027.

Don't forget the ISA has only existed in frozen form since July 2019, just over four years.

Being in IT tech all my career, I've learnt to not trust news from the future. I will believe it when I will hold those things in my hands. As things stand right now, RV loses even to ARM, not to mention x86, in just about any important metric.

[brucehoult]

Being in IT tech all my career

Me too, 39 years post-university experience.  Well, programmer, only incidentally managing machines and networks when I was the sole IT person in various small companies.

I've learnt to not trust news from the future. I will believe it when I will hold those things in my hands.

Which you will be able to do very soon, if you choose to.

There are many things in computing which are pipe dreams, vapour, even scams.

CPU cores are not one of those.

Perhaps you don't understand that at the point a new CPU core is formally announced (that is: the vendor is ready to sell licenses) it has already been completely designed (a several year process), tested in an RTL simulator (dhrystone and coremark can be run at this stage), tested in a cycle-accurate FPGA (or similar) framework booting Linux and running SPEC and other workloads of interest.

There is pretty much zero doubt that the logical design works as promised (some errata almost always slip though, but not show-stoppers).

The process of implementing the design in silicon is then a straightforward one, though several years of work for a large team. Assuming you're targeting a relatively mature chip process (i.e. not 3nm or something but, say, 7+ at this point) there is very very little chance of it not working, assuming the company doesn't run out of money.

As things stand right now, RV loses even to ARM, not to mention x86, in just about any important metric.

Yes, right now, when the cores in the market are ones designed before the ISA was even finalised, and announced right around the time the ISA was ratified.

Ignoring all the new cores that have gone into the pipeline since then and will appear in physical form in the next couple of years is foolishness.

[brucehoult]

Apple bought PA Semi in 2008, but the M1 didn't ship until 2020.  Why did it take so long, and why would the RISC-V startups be able to move faster, especially when they don't have the advantage of unlimited money?

Because in 2008 no one in the world had ever built anything like an M1.

In 2023, the main engineers at multiple RISC-V startups already built the M1.

[brucehoult]

Troll.

[asmi]

CPU cores are not one of those.

I've heard these songs for a long time. But the only thing which came out of those are overpriced devboards which cost more than several x86 PCs each of which would tear CPU on those devboards apart without breaking the sweat. Sorry to be a downer, but I'm tired of this BS.

Don't get me wrong - everyone who reads this forum knows that I myself is a big fan of RV and even have a couple of my very own softcores which I made for fun and learning, but we need to call spade a spade - so far all we have is a mountain of hype and a handful of feeble SoCs which can't get anywhere near their competitors, all while costing ridiculous amounts of money.

[brucehoult]

CPU cores are not one of those.

I've heard these songs for a long time. But the only thing which came out of those are overpriced devboards which cost more than several x86 PCs each of which would tear CPU on those devboards apart without breaking the sweat. Sorry to be a downer, but I'm tired of this BS.

I don't know what kind of x86 PC (other than 2nd hand) you can get for the price of a $39 2 GB Milk-V Mars (quad core 1.5 GHz, similar to an Arm A55 other than lacking SIMD)

As for performance, they do exactly what 1) the makers claim, and 2) what you'd expect given the (well publicised) microarchitecture and clock speed.

If you expect something with similar architecture to a Pentium or PowerPC 603 (though with 10-20x higher clock speed) to perform like a 2020s 4-5 GHz OoO x86 then that's entirely your problem and lack of understanding.

RISC-V with performance similar to modern x86 or Apple is coming around 2026-2027 and ALWAYS HAS BEEN.

No one (with any knowledge) has ever claimed any differently.

[DiTBho]

I don't know what kind of x86 PC (other than 2nd hand) you can get for the price of ...

most likely a ZimaBlade 
(sarc, sorry)

[asmi]

I don't know what kind of x86 PC (other than 2nd hand) you can get for the price of a $39 2 GB Milk-V Mars (quad core 1.5 GHz, similar to an Arm A55 other than lacking SIMD)

You don't need any x86 for that, as even previous gen RaspPi will tear this POS to pieces. And PCIE 2.0? Seriously? Someone tell those guys that it's almost 2024 now, not 2010

As for performance, they do exactly what 1) the makers claim, and 2) what you'd expect given the (well publicised) microarchitecture and clock speed.

Did they claim that this SoC is going to be a POS? I suspect not. But here we are. It takes a special talent to design something which is 1) slower than prev-gen RPi, AND 2) has worse efficiency all at the same time! Pure waste of sand!

RISC-V with performance similar to modern x86 or Apple is coming around 2026-2027 and ALWAYS HAS BEEN.

This is the first time ever I hear about those years. But I've been getting marketing emails from SiFive for years and each and every core was touted as a "most powerful ever!", "most efficient!" and "super-fast!", and other Want to take any guess as to what they really turned out to be?
Yeah, that's why I will believe it when I will hold the device in my hands. Until that happens, this is nothing but BS and hype.

[brucehoult]

I don't know what kind of x86 PC (other than 2nd hand) you can get for the price of a $39 2 GB Milk-V Mars (quad core 1.5 GHz, similar to an Arm A55 other than lacking SIMD)

You don't need any x86 for that, as even previous gen RaspPi will tear this POS to pieces.

Not on generic C code it won't.  On things using NEON, certainly, because this generation of RISC-V doesn't yet have SIMD or Vector.

Feel free to browse my own personal primes benchmark, for example, which I created in 2016 for comparing Pi 3 to Odroid XU4 and i7 4770 -- before I even knew RISC-V existed.

https://hoult.org/primes.txt

I'll extract a few results here

Code: [Select]

10.430 sec Sipeed LM4A TH1520 4x C910 @1.848 GHz 216 bytes  19.3 billion clocks
10.851 sec Sophon SG2042 64x C910 RV64 @1.8? GHz 216 bytes  19.3 billion clocks
11.445 sec Odroid XU4 A15 @ 2 GHz T32            204 bytes  22.9 billion clocks
12.115 sec Pi4 Cortex A72 @ 1.5 GHz A64          300 bytes  18.2 billion clocks
14.885 sec VisionFive 2 U74 _zba_zbb @ 1.5 GHz   214 bytes  22.3 billion clocks
19.500 sec Odroid C2 A53 @ 1.536 GHz A64         276 bytes  30.0 billion clocks
27.480 sec HiFive Unleashed RISCV U54 @ 1.45 GHz 228 bytes  39.8 billion clocks
30.420 sec Pi3 Cortex A53 @ 1.2 GHz T32          204 bytes  36.5 billion clocks
36.652 sec Allwinner D1 C906 RV64 @ 1.008 GHz    224 bytes  36.9 billion clocks
47.910 sec Pi2 Cortex A7 @ 900 MHz T32           204 bytes  42.1 billion clocks

You'll notice the Sipeed Lichee Pi 4A is faster than Pi 4, and the VisionFive 2 (Mars will be the same) easily beats Arm A53 boards such as Odroid C2 and Pi 3 (your "previous generation", I assume).

I've been getting marketing emails from SiFive for years and each and every core was touted as a "most powerful ever!", "most efficient!" and "super-fast!", and other

The fastest SiFive have ever made, yes.

If you interpret it to mean the fastest computer anyone has ever made then you are simply an idiot.

Want to take any guess as to what they really turned out to be?

Sure. They gave basically the exact Dhrystone, Coremark, SPEC results as claimed at the time the core was announced, four years earlier?

Which you are free to compare to the same benchmarks on another system before you buy, to correctly set your expectations.

[asmi]

Pi 3 (your "previous generation", I assume).

previous-gen RPi is RPi 4. RPi5 is now out in case you didn't notice.

The fastest SiFive have ever made, yes.

Curiously they tended to omit that part.

If you interpret it to mean the fastest computer anyone has ever made then you are simply an idiot.

Personal attacks don't help you making your point. And I simply read what is written.

Sure. They gave basically the exact Dhrystone, Coremark, SPEC results as claimed at the time the core was announced, four years earlier?

No - they turned out to be garbage, overpriced turds.